drm/i915/cnl: Dump the right pll registers when dumping pipe config.

Different from SKL we don't need ctrl1 and cfgcr2, but
we need to dump cfgcr0 and cfgcr1 instead.

v2: rebase and commit message

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170810224525.18278-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 2f7b0e64f6284553ec151f00605dab2b94908003..a2a3d93d67bd252a3c9d137bedb66be26816bd23 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
        return pll;
 }
 
+static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
+                             struct intel_dpll_hw_state *hw_state)
+{
+       DRM_DEBUG_KMS("dpll_hw_state: "
+                     "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
+                     hw_state->cfgcr0,
+                     hw_state->cfgcr1);
+}
+
 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
        .enable = cnl_ddi_pll_enable,
        .disable = cnl_ddi_pll_disable,
@@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = {
 static const struct intel_dpll_mgr cnl_pll_mgr = {
        .dpll_info = cnl_plls,
        .get_dpll = cnl_get_dpll,
-       .dump_hw_state = skl_dump_hw_state,
+       .dump_hw_state = cnl_dump_hw_state,
 };
 
 /**