ASPEED BMCs
M: Cédric Le Goater <clg@kaod.org>
M: Peter Maydell <peter.maydell@linaro.org>
-R: Andrew Jeffery <andrew@aj.id.au>
+R: Andrew Jeffery <andrew@codeconstruct.com.au>
R: Joel Stanley <joel@jms.id.au>
L: qemu-arm@nongnu.org
S: Maintained
MachineState parent_obj;
/* Public */
- AspeedSoCState soc;
+ AspeedSoCState *soc;
MemoryRegion boot_rom;
bool mmio_exec;
uint32_t uart_chosen;
static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
&error_abort);
static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
{
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
- AspeedSoCState *s = &bmc->soc;
+ AspeedSoCState *s = bmc->soc;
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
int i;
NICInfo *nd = &nd_table[0];
- object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
- sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ sc = ASPEED_SOC_GET_CLASS(bmc->soc);
/*
* This will error out if the RAM size is not supported by the
* memory controller of the SoC.
*/
- object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+ object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
&error_fatal);
for (i = 0; i < sc->macs_num; i++) {
if ((amc->macs_mask & (1 << i)) && nd->used) {
qemu_check_nic_model(nd, TYPE_FTGMAC100);
- qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+ qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
nd++;
}
}
- object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+ object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+ object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
&error_abort);
- object_property_set_link(OBJECT(&bmc->soc), "memory",
+ object_property_set_link(OBJECT(bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
- object_property_set_link(OBJECT(&bmc->soc), "dram",
+ object_property_set_link(OBJECT(bmc->soc), "dram",
OBJECT(machine->ram), &error_abort);
if (machine->kernel_filename) {
/*
* that runs to unlock the SCU. In this case set the default to
* be unlocked as the kernel expects
*/
- object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+ object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
ASPEED_SCU_PROT_KEY, &error_abort);
}
connect_serial_hds_to_uarts(bmc);
- qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
if (defaults_enabled()) {
- aspeed_board_init_flashes(&bmc->soc.fmc,
+ aspeed_board_init_flashes(&bmc->soc->fmc,
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
amc->num_cs, 0);
- aspeed_board_init_flashes(&bmc->soc.spi[0],
+ aspeed_board_init_flashes(&bmc->soc->spi[0],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
1, amc->num_cs);
}
amc->i2c_init(bmc);
}
- for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
- sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+ for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+ sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
drive_get(IF_SD, 0, i));
}
- if (bmc->soc.emmc.num_slots) {
- sdhci_attach_drive(&bmc->soc.emmc.slots[0],
- drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+ if (bmc->soc->emmc.num_slots) {
+ sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+ drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
}
if (!bmc->mmio_exec) {
- DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+ DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
if (fmc0) {
- uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+ uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
aspeed_install_boot_rom(bmc, fmc0, rom_size);
}
}
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
DeviceState *dev;
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/*
* The quanta-q71l platform expects tmp75s which are compatible with
static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
* good enough */
static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* bus 2 : */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
{14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
{15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
};
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
DeviceState *dev;
LEDState *led;
static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
DeviceState *dev;
dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *i2c_mux;
/* The at24c256 */
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *i2c_mux;
at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[144] = {};
for (int i = 0; i < 16; i++) {
static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[13] = {};
for (int i = 0; i < 13; i++) {
if ((i == 8) || (i == 11)) {
static void fby35_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CBus *i2c[16];
for (int i = 0; i < 16; i++) {
static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
}
static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
I2CSlave *therm_mux, *cpuvr_mux;
/* Create the generic DC-SCM hardware */
static void fby35_reset(MachineState *state, ShutdownCause reason)
{
AspeedMachineState *bmc = ASPEED_MACHINE(state);
- AspeedGPIOState *gpio = &bmc->soc.gpio;
+ AspeedGPIOState *gpio = &bmc->soc->gpio;
qemu_devices_reset(reason);
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
- object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
- qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
- object_property_set_link(OBJECT(&bmc->soc), "memory",
+ object_property_set_link(OBJECT(bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
connect_serial_hds_to_uarts(bmc);
- qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
- aspeed_board_init_flashes(&bmc->soc.fmc,
+ aspeed_board_init_flashes(&bmc->soc->fmc,
bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
amc->num_cs,
0);
- aspeed_board_init_flashes(&bmc->soc.spi[0],
+ aspeed_board_init_flashes(&bmc->soc->spi[0],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, amc->num_cs);
- aspeed_board_init_flashes(&bmc->soc.spi[1],
+ aspeed_board_init_flashes(&bmc->soc->spi[1],
bmc->spi_model ? bmc->spi_model : amc->spi_model,
amc->num_cs, (amc->num_cs * 2));
static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
{
- AspeedSoCState *soc = &bmc->soc;
+ AspeedSoCState *soc = bmc->soc;
/* U10 24C08 connects to SDA/SCL Group 1 by default */
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
}
static void aspeed_soc_ast1030_init(Object *obj)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
char socname[8];
g_assert_not_reached();
}
- object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
0x40000);
/* AST1030 CPU Core */
- armv7m = DEVICE(&s->armv7m);
+ armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
- object_property_set_link(OBJECT(&s->armv7m), "memory",
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
- CPU(s->armv7m.cpu)->cpu_index);
+ CPU(a->armv7m.cpu)->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err != NULL) {
error_propagate(errp, err);
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I2C] + i);
/* The AST1030 I2C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I3C] + i);
/* The AST1030 I3C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&s->armv7m),
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* UART */
sc->get_irq = aspeed_soc_ast1030_get_irq;
}
-static const TypeInfo aspeed_soc_ast1030_type_info = {
- .name = "ast1030-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_size = sizeof(AspeedSoCState),
- .instance_init = aspeed_soc_ast1030_init,
- .class_init = aspeed_soc_ast1030_class_init,
- .class_size = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+ {
+ .name = TYPE_ASPEED10X0_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed10x0SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast1030-a1",
+ .parent = TYPE_ASPEED10X0_SOC,
+ .instance_init = aspeed_soc_ast1030_init,
+ .class_init = aspeed_soc_ast1030_class_init,
+ },
};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
--- /dev/null
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+
+#define ASPEED_SOC_IOMEM_SIZE 0x00200000
+
+static const hwaddr aspeed_soc_ast2400_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
+ [ASPEED_DEV_IOMEM] = 0x1E600000,
+ [ASPEED_DEV_FMC] = 0x1E620000,
+ [ASPEED_DEV_SPI1] = 0x1E630000,
+ [ASPEED_DEV_EHCI1] = 0x1E6A1000,
+ [ASPEED_DEV_VIC] = 0x1E6C0000,
+ [ASPEED_DEV_SDMC] = 0x1E6E0000,
+ [ASPEED_DEV_SCU] = 0x1E6E2000,
+ [ASPEED_DEV_HACE] = 0x1E6E3000,
+ [ASPEED_DEV_XDMA] = 0x1E6E7000,
+ [ASPEED_DEV_VIDEO] = 0x1E700000,
+ [ASPEED_DEV_ADC] = 0x1E6E9000,
+ [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SDHCI] = 0x1E740000,
+ [ASPEED_DEV_GPIO] = 0x1E780000,
+ [ASPEED_DEV_RTC] = 0x1E781000,
+ [ASPEED_DEV_TIMER1] = 0x1E782000,
+ [ASPEED_DEV_WDT] = 0x1E785000,
+ [ASPEED_DEV_PWM] = 0x1E786000,
+ [ASPEED_DEV_LPC] = 0x1E789000,
+ [ASPEED_DEV_IBT] = 0x1E789140,
+ [ASPEED_DEV_I2C] = 0x1E78A000,
+ [ASPEED_DEV_PECI] = 0x1E78B000,
+ [ASPEED_DEV_ETH1] = 0x1E660000,
+ [ASPEED_DEV_ETH2] = 0x1E680000,
+ [ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
+ [ASPEED_DEV_UART5] = 0x1E784000,
+ [ASPEED_DEV_VUART] = 0x1E787000,
+ [ASPEED_DEV_SDRAM] = 0x40000000,
+};
+
+static const hwaddr aspeed_soc_ast2500_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
+ [ASPEED_DEV_IOMEM] = 0x1E600000,
+ [ASPEED_DEV_FMC] = 0x1E620000,
+ [ASPEED_DEV_SPI1] = 0x1E630000,
+ [ASPEED_DEV_SPI2] = 0x1E631000,
+ [ASPEED_DEV_EHCI1] = 0x1E6A1000,
+ [ASPEED_DEV_EHCI2] = 0x1E6A3000,
+ [ASPEED_DEV_VIC] = 0x1E6C0000,
+ [ASPEED_DEV_SDMC] = 0x1E6E0000,
+ [ASPEED_DEV_SCU] = 0x1E6E2000,
+ [ASPEED_DEV_HACE] = 0x1E6E3000,
+ [ASPEED_DEV_XDMA] = 0x1E6E7000,
+ [ASPEED_DEV_ADC] = 0x1E6E9000,
+ [ASPEED_DEV_VIDEO] = 0x1E700000,
+ [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SDHCI] = 0x1E740000,
+ [ASPEED_DEV_GPIO] = 0x1E780000,
+ [ASPEED_DEV_RTC] = 0x1E781000,
+ [ASPEED_DEV_TIMER1] = 0x1E782000,
+ [ASPEED_DEV_WDT] = 0x1E785000,
+ [ASPEED_DEV_PWM] = 0x1E786000,
+ [ASPEED_DEV_LPC] = 0x1E789000,
+ [ASPEED_DEV_IBT] = 0x1E789140,
+ [ASPEED_DEV_I2C] = 0x1E78A000,
+ [ASPEED_DEV_PECI] = 0x1E78B000,
+ [ASPEED_DEV_ETH1] = 0x1E660000,
+ [ASPEED_DEV_ETH2] = 0x1E680000,
+ [ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
+ [ASPEED_DEV_UART5] = 0x1E784000,
+ [ASPEED_DEV_VUART] = 0x1E787000,
+ [ASPEED_DEV_SDRAM] = 0x80000000,
+};
+
+static const int aspeed_soc_ast2400_irqmap[] = {
+ [ASPEED_DEV_UART1] = 9,
+ [ASPEED_DEV_UART2] = 32,
+ [ASPEED_DEV_UART3] = 33,
+ [ASPEED_DEV_UART4] = 34,
+ [ASPEED_DEV_UART5] = 10,
+ [ASPEED_DEV_VUART] = 8,
+ [ASPEED_DEV_FMC] = 19,
+ [ASPEED_DEV_EHCI1] = 5,
+ [ASPEED_DEV_EHCI2] = 13,
+ [ASPEED_DEV_SDMC] = 0,
+ [ASPEED_DEV_SCU] = 21,
+ [ASPEED_DEV_ADC] = 31,
+ [ASPEED_DEV_GPIO] = 20,
+ [ASPEED_DEV_RTC] = 22,
+ [ASPEED_DEV_TIMER1] = 16,
+ [ASPEED_DEV_TIMER2] = 17,
+ [ASPEED_DEV_TIMER3] = 18,
+ [ASPEED_DEV_TIMER4] = 35,
+ [ASPEED_DEV_TIMER5] = 36,
+ [ASPEED_DEV_TIMER6] = 37,
+ [ASPEED_DEV_TIMER7] = 38,
+ [ASPEED_DEV_TIMER8] = 39,
+ [ASPEED_DEV_WDT] = 27,
+ [ASPEED_DEV_PWM] = 28,
+ [ASPEED_DEV_LPC] = 8,
+ [ASPEED_DEV_I2C] = 12,
+ [ASPEED_DEV_PECI] = 15,
+ [ASPEED_DEV_ETH1] = 2,
+ [ASPEED_DEV_ETH2] = 3,
+ [ASPEED_DEV_XDMA] = 6,
+ [ASPEED_DEV_SDHCI] = 26,
+ [ASPEED_DEV_HACE] = 4,
+};
+
+#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
+
+static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed2400SoCState *a = ASPEED2400_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
+}
+
+static void aspeed_ast2400_soc_init(Object *obj)
+{
+ Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+ char socname[8];
+ char typename[64];
+
+ if (sscanf(sc->name, "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ for (i = 0; i < sc->num_cpus; i++) {
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
+ }
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ sc->silicon_rev);
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
+ "hw-strap1");
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
+ "hw-strap2");
+ object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
+ "hw-prot-key");
+
+ object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
+
+ object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
+
+ snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
+ object_initialize_child(obj, "adc", &s->adc, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
+ object_initialize_child(obj, "i2c", &s->i2c, typename);
+
+ object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
+
+ snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
+ object_initialize_child(obj, "fmc", &s->fmc, typename);
+
+ for (i = 0; i < sc->spis_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
+ }
+
+ for (i = 0; i < sc->ehcis_num; i++) {
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
+ }
+
+ snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
+ object_initialize_child(obj, "sdmc", &s->sdmc, typename);
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
+ "ram-size");
+
+ for (i = 0; i < sc->wdts_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
+ object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
+ }
+
+ for (i = 0; i < sc->macs_num; i++) {
+ object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
+ TYPE_FTGMAC100);
+ }
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
+ object_initialize_child(obj, "xdma", &s->xdma, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
+ object_initialize_child(obj, "gpio", &s->gpio, typename);
+
+ object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
+
+ object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
+
+ /* Init sd card slot class here so that they're under the correct parent */
+ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
+ object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
+ TYPE_SYSBUS_SDHCI);
+ }
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
+
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+ object_initialize_child(obj, "hace", &s->hace, typename);
+
+ object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
+}
+
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
+{
+ int i;
+ Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ Error *err = NULL;
+ g_autofree char *sram_name = NULL;
+
+ /* Default boot region (SPI memory or ROMs) */
+ memory_region_init(&s->spi_boot_container, OBJECT(s),
+ "aspeed.spi_boot_container", 0x10000000);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
+ &s->spi_boot_container);
+
+ /* IO space */
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
+ sc->memmap[ASPEED_DEV_IOMEM],
+ ASPEED_SOC_IOMEM_SIZE);
+
+ /* Video engine stub */
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
+ sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
+
+ /* CPU */
+ for (i = 0; i < sc->num_cpus; i++) {
+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",
+ OBJECT(s->memory), &error_abort);
+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
+ return;
+ }
+ }
+
+ /* SRAM */
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
+ memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+
+ /* VIC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
+ qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
+
+ /* RTC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
+
+ /* Timer */
+ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ sc->memmap[ASPEED_DEV_TIMER1]);
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
+ }
+
+ /* ADC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+
+ /* UART */
+ if (!aspeed_soc_uart_realize(s, errp)) {
+ return;
+ }
+
+ /* I2C */
+ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
+
+ /* PECI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
+ sc->memmap[ASPEED_DEV_PECI]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
+
+ /* FMC, The number of CS is set at the board level */
+ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+
+ /* Set up an alias on the FMC CE0 region (boot default) */
+ MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
+ memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
+ fmc0_mmio, 0, memory_region_size(fmc0_mmio));
+ memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
+
+ /* SPI */
+ for (i = 0; i < sc->spis_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ sc->memmap[ASPEED_DEV_SPI1 + i]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ }
+
+ /* EHCI */
+ for (i = 0; i < sc->ehcis_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ sc->memmap[ASPEED_DEV_EHCI1 + i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
+ }
+
+ /* SDMC - SDRAM Memory Controller */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ sc->memmap[ASPEED_DEV_SDMC]);
+
+ /* Watch dog */
+ for (i = 0; i < sc->wdts_num; i++) {
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
+
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ }
+
+ /* RAM */
+ if (!aspeed_soc_dram_init(s, errp)) {
+ return;
+ }
+
+ /* Net */
+ for (i = 0; i < sc->macs_num; i++) {
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ sc->memmap[ASPEED_DEV_ETH1 + i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
+ }
+
+ /* XDMA */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
+ sc->memmap[ASPEED_DEV_XDMA]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
+
+ /* GPIO */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ sc->memmap[ASPEED_DEV_GPIO]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+
+ /* SDHCI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+ sc->memmap[ASPEED_DEV_SDHCI]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+
+ /* LPC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+
+ /* Connect the LPC IRQ to the VIC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+
+ /*
+ * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
+ * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
+ * contrast, on the AST2600, the subdevice IRQs are connected straight to
+ * the GIC).
+ *
+ * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
+ * to the VIC is at offset 0.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
+
+ /* HACE */
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ sc->memmap[ASPEED_DEV_HACE]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+}
+
+static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_ast2400_soc_realize;
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
+
+ sc->name = "ast2400-a1";
+ sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ sc->silicon_rev = AST2400_A1_SILICON_REV;
+ sc->sram_size = 0x8000;
+ sc->spis_num = 1;
+ sc->ehcis_num = 1;
+ sc->wdts_num = 2;
+ sc->macs_num = 2;
+ sc->uarts_num = 5;
+ sc->irqmap = aspeed_soc_ast2400_irqmap;
+ sc->memmap = aspeed_soc_ast2400_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast2400_get_irq;
+}
+
+static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_ast2400_soc_realize;
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
+
+ sc->name = "ast2500-a1";
+ sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ sc->silicon_rev = AST2500_A1_SILICON_REV;
+ sc->sram_size = 0x9000;
+ sc->spis_num = 2;
+ sc->ehcis_num = 2;
+ sc->wdts_num = 3;
+ sc->macs_num = 2;
+ sc->uarts_num = 5;
+ sc->irqmap = aspeed_soc_ast2500_irqmap;
+ sc->memmap = aspeed_soc_ast2500_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast2400_get_irq;
+}
+
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+ {
+ .name = TYPE_ASPEED2400_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_init = aspeed_ast2400_soc_init,
+ .instance_size = sizeof(Aspeed2400SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2400-a1",
+ .parent = TYPE_ASPEED2400_SOC,
+ .class_init = aspeed_soc_ast2400_class_init,
+ }, {
+ .name = "ast2500-a1",
+ .parent = TYPE_ASPEED2400_SOC,
+ .class_init = aspeed_soc_ast2500_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_ast2400_types)
static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
{
+ Aspeed2600SoCState *a = ASPEED2600_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+ return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
}
static void aspeed_soc_ast2600_init(Object *obj)
{
+ Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
- object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+ object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
TYPE_A15MPCORE_PRIV);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
{
int i;
+ Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
if (sc->num_cpus > 1) {
- object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+ object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
ASPEED_A7MPCORE_ADDR, &error_abort);
}
- object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+ object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
aspeed_calc_affinity(i), &error_abort);
- object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+ object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
&error_abort);
- object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+ object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
&error_abort);
- object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+ object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
&error_abort);
- object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",
OBJECT(s->memory), &error_abort);
- if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
return;
}
}
/* A7MPCORE */
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+ object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+ object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+ sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
for (i = 0; i < sc->num_cpus; i++) {
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(&s->cpu[i]);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+ DeviceState *d = DEVICE(&a->cpu[i]);
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
}
/* SRAM */
- sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I2C] + i);
/* The AST2600 I2C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
* offset 0.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* HACE */
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I3C] + i);
/* The AST2600 I3C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
sc->get_irq = aspeed_soc_ast2600_get_irq;
}
-static const TypeInfo aspeed_soc_ast2600_type_info = {
- .name = "ast2600-a3",
- .parent = TYPE_ASPEED_SOC,
- .instance_size = sizeof(AspeedSoCState),
- .instance_init = aspeed_soc_ast2600_init,
- .class_init = aspeed_soc_ast2600_class_init,
- .class_size = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+ {
+ .name = TYPE_ASPEED2600_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed2600SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2600-a3",
+ .parent = TYPE_ASPEED2600_SOC,
+ .instance_init = aspeed_soc_ast2600_init,
+ .class_init = aspeed_soc_ast2600_class_init,
+ },
};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
+++ /dev/null
-/*
- * ASPEED SoC family
- *
- * Andrew Jeffery <andrew@aj.id.au>
- * Jeremy Kerr <jk@ozlabs.org>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later. See
- * the COPYING file in the top-level directory.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "qapi/error.h"
-#include "hw/misc/unimp.h"
-#include "hw/arm/aspeed_soc.h"
-#include "hw/char/serial.h"
-#include "qemu/module.h"
-#include "qemu/error-report.h"
-#include "hw/i2c/aspeed_i2c.h"
-#include "net/net.h"
-#include "sysemu/sysemu.h"
-
-#define ASPEED_SOC_IOMEM_SIZE 0x00200000
-
-static const hwaddr aspeed_soc_ast2400_memmap[] = {
- [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
- [ASPEED_DEV_IOMEM] = 0x1E600000,
- [ASPEED_DEV_FMC] = 0x1E620000,
- [ASPEED_DEV_SPI1] = 0x1E630000,
- [ASPEED_DEV_EHCI1] = 0x1E6A1000,
- [ASPEED_DEV_VIC] = 0x1E6C0000,
- [ASPEED_DEV_SDMC] = 0x1E6E0000,
- [ASPEED_DEV_SCU] = 0x1E6E2000,
- [ASPEED_DEV_HACE] = 0x1E6E3000,
- [ASPEED_DEV_XDMA] = 0x1E6E7000,
- [ASPEED_DEV_VIDEO] = 0x1E700000,
- [ASPEED_DEV_ADC] = 0x1E6E9000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
- [ASPEED_DEV_SDHCI] = 0x1E740000,
- [ASPEED_DEV_GPIO] = 0x1E780000,
- [ASPEED_DEV_RTC] = 0x1E781000,
- [ASPEED_DEV_TIMER1] = 0x1E782000,
- [ASPEED_DEV_WDT] = 0x1E785000,
- [ASPEED_DEV_PWM] = 0x1E786000,
- [ASPEED_DEV_LPC] = 0x1E789000,
- [ASPEED_DEV_IBT] = 0x1E789140,
- [ASPEED_DEV_I2C] = 0x1E78A000,
- [ASPEED_DEV_PECI] = 0x1E78B000,
- [ASPEED_DEV_ETH1] = 0x1E660000,
- [ASPEED_DEV_ETH2] = 0x1E680000,
- [ASPEED_DEV_UART1] = 0x1E783000,
- [ASPEED_DEV_UART2] = 0x1E78D000,
- [ASPEED_DEV_UART3] = 0x1E78E000,
- [ASPEED_DEV_UART4] = 0x1E78F000,
- [ASPEED_DEV_UART5] = 0x1E784000,
- [ASPEED_DEV_VUART] = 0x1E787000,
- [ASPEED_DEV_SDRAM] = 0x40000000,
-};
-
-static const hwaddr aspeed_soc_ast2500_memmap[] = {
- [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
- [ASPEED_DEV_IOMEM] = 0x1E600000,
- [ASPEED_DEV_FMC] = 0x1E620000,
- [ASPEED_DEV_SPI1] = 0x1E630000,
- [ASPEED_DEV_SPI2] = 0x1E631000,
- [ASPEED_DEV_EHCI1] = 0x1E6A1000,
- [ASPEED_DEV_EHCI2] = 0x1E6A3000,
- [ASPEED_DEV_VIC] = 0x1E6C0000,
- [ASPEED_DEV_SDMC] = 0x1E6E0000,
- [ASPEED_DEV_SCU] = 0x1E6E2000,
- [ASPEED_DEV_HACE] = 0x1E6E3000,
- [ASPEED_DEV_XDMA] = 0x1E6E7000,
- [ASPEED_DEV_ADC] = 0x1E6E9000,
- [ASPEED_DEV_VIDEO] = 0x1E700000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
- [ASPEED_DEV_SDHCI] = 0x1E740000,
- [ASPEED_DEV_GPIO] = 0x1E780000,
- [ASPEED_DEV_RTC] = 0x1E781000,
- [ASPEED_DEV_TIMER1] = 0x1E782000,
- [ASPEED_DEV_WDT] = 0x1E785000,
- [ASPEED_DEV_PWM] = 0x1E786000,
- [ASPEED_DEV_LPC] = 0x1E789000,
- [ASPEED_DEV_IBT] = 0x1E789140,
- [ASPEED_DEV_I2C] = 0x1E78A000,
- [ASPEED_DEV_PECI] = 0x1E78B000,
- [ASPEED_DEV_ETH1] = 0x1E660000,
- [ASPEED_DEV_ETH2] = 0x1E680000,
- [ASPEED_DEV_UART1] = 0x1E783000,
- [ASPEED_DEV_UART2] = 0x1E78D000,
- [ASPEED_DEV_UART3] = 0x1E78E000,
- [ASPEED_DEV_UART4] = 0x1E78F000,
- [ASPEED_DEV_UART5] = 0x1E784000,
- [ASPEED_DEV_VUART] = 0x1E787000,
- [ASPEED_DEV_SDRAM] = 0x80000000,
-};
-
-static const int aspeed_soc_ast2400_irqmap[] = {
- [ASPEED_DEV_UART1] = 9,
- [ASPEED_DEV_UART2] = 32,
- [ASPEED_DEV_UART3] = 33,
- [ASPEED_DEV_UART4] = 34,
- [ASPEED_DEV_UART5] = 10,
- [ASPEED_DEV_VUART] = 8,
- [ASPEED_DEV_FMC] = 19,
- [ASPEED_DEV_EHCI1] = 5,
- [ASPEED_DEV_EHCI2] = 13,
- [ASPEED_DEV_SDMC] = 0,
- [ASPEED_DEV_SCU] = 21,
- [ASPEED_DEV_ADC] = 31,
- [ASPEED_DEV_GPIO] = 20,
- [ASPEED_DEV_RTC] = 22,
- [ASPEED_DEV_TIMER1] = 16,
- [ASPEED_DEV_TIMER2] = 17,
- [ASPEED_DEV_TIMER3] = 18,
- [ASPEED_DEV_TIMER4] = 35,
- [ASPEED_DEV_TIMER5] = 36,
- [ASPEED_DEV_TIMER6] = 37,
- [ASPEED_DEV_TIMER7] = 38,
- [ASPEED_DEV_TIMER8] = 39,
- [ASPEED_DEV_WDT] = 27,
- [ASPEED_DEV_PWM] = 28,
- [ASPEED_DEV_LPC] = 8,
- [ASPEED_DEV_I2C] = 12,
- [ASPEED_DEV_PECI] = 15,
- [ASPEED_DEV_ETH1] = 2,
- [ASPEED_DEV_ETH2] = 3,
- [ASPEED_DEV_XDMA] = 6,
- [ASPEED_DEV_SDHCI] = 26,
- [ASPEED_DEV_HACE] = 4,
-};
-
-#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
-
-static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-
- return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
-}
-
-static void aspeed_soc_init(Object *obj)
-{
- AspeedSoCState *s = ASPEED_SOC(obj);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- int i;
- char socname[8];
- char typename[64];
-
- if (sscanf(sc->name, "%7s", socname) != 1) {
- g_assert_not_reached();
- }
-
- for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
- }
-
- snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
- object_initialize_child(obj, "scu", &s->scu, typename);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
- sc->silicon_rev);
- object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
- "hw-strap1");
- object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
- "hw-strap2");
- object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
- "hw-prot-key");
-
- object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
-
- object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
-
- snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
- object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
-
- snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
- object_initialize_child(obj, "adc", &s->adc, typename);
-
- snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
- object_initialize_child(obj, "i2c", &s->i2c, typename);
-
- object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
-
- snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
- object_initialize_child(obj, "fmc", &s->fmc, typename);
-
- for (i = 0; i < sc->spis_num; i++) {
- snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
- object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
- }
-
- for (i = 0; i < sc->ehcis_num; i++) {
- object_initialize_child(obj, "ehci[*]", &s->ehci[i],
- TYPE_PLATFORM_EHCI);
- }
-
- snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
- object_initialize_child(obj, "sdmc", &s->sdmc, typename);
- object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
- "ram-size");
-
- for (i = 0; i < sc->wdts_num; i++) {
- snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
- object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
- }
-
- for (i = 0; i < sc->macs_num; i++) {
- object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
- TYPE_FTGMAC100);
- }
-
- for (i = 0; i < sc->uarts_num; i++) {
- object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
- }
-
- snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
- object_initialize_child(obj, "xdma", &s->xdma, typename);
-
- snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
- object_initialize_child(obj, "gpio", &s->gpio, typename);
-
- object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
-
- object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
-
- /* Init sd card slot class here so that they're under the correct parent */
- for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
- object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
- TYPE_SYSBUS_SDHCI);
- }
-
- object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
-
- snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
- object_initialize_child(obj, "hace", &s->hace, typename);
-
- object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
-}
-
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
-{
- int i;
- AspeedSoCState *s = ASPEED_SOC(dev);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- Error *err = NULL;
- g_autofree char *sram_name = NULL;
-
- /* Default boot region (SPI memory or ROMs) */
- memory_region_init(&s->spi_boot_container, OBJECT(s),
- "aspeed.spi_boot_container", 0x10000000);
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
- &s->spi_boot_container);
-
- /* IO space */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
- sc->memmap[ASPEED_DEV_IOMEM],
- ASPEED_SOC_IOMEM_SIZE);
-
- /* Video engine stub */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
- sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
-
- /* CPU */
- for (i = 0; i < sc->num_cpus; i++) {
- object_property_set_link(OBJECT(&s->cpu[i]), "memory",
- OBJECT(s->memory), &error_abort);
- if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
- return;
- }
- }
-
- /* SRAM */
- sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
- memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
- memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
-
- /* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
-
- /* VIC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
- qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
-
- /* RTC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
-
- /* Timer */
- object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
- sc->memmap[ASPEED_DEV_TIMER1]);
- for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
- qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
- }
-
- /* ADC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
-
- /* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
- }
-
- /* I2C */
- object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
-
- /* PECI */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
- sc->memmap[ASPEED_DEV_PECI]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
-
- /* FMC, The number of CS is set at the board level */
- object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
- ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
-
- /* Set up an alias on the FMC CE0 region (boot default) */
- MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
- memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
- fmc0_mmio, 0, memory_region_size(fmc0_mmio));
- memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
-
- /* SPI */
- for (i = 0; i < sc->spis_num; i++) {
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
- sc->memmap[ASPEED_DEV_SPI1 + i]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
- ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
- }
-
- /* EHCI */
- for (i = 0; i < sc->ehcis_num; i++) {
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
- sc->memmap[ASPEED_DEV_EHCI1 + i]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
- }
-
- /* SDMC - SDRAM Memory Controller */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
- sc->memmap[ASPEED_DEV_SDMC]);
-
- /* Watch dog */
- for (i = 0; i < sc->wdts_num; i++) {
- AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
- hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
-
- object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
- }
-
- /* RAM */
- if (!aspeed_soc_dram_init(s, errp)) {
- return;
- }
-
- /* Net */
- for (i = 0; i < sc->macs_num; i++) {
- object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- sc->memmap[ASPEED_DEV_ETH1 + i]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
- }
-
- /* XDMA */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
- sc->memmap[ASPEED_DEV_XDMA]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
-
- /* GPIO */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
- sc->memmap[ASPEED_DEV_GPIO]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
-
- /* SDHCI */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
- sc->memmap[ASPEED_DEV_SDHCI]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
-
- /* LPC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
-
- /* Connect the LPC IRQ to the VIC */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
-
- /*
- * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
- * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
- * contrast, on the AST2600, the subdevice IRQs are connected straight to
- * the GIC).
- *
- * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
- * to the VIC is at offset 0.
- */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
-
- /* HACE */
- object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
- sc->memmap[ASPEED_DEV_HACE]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
-}
-static Property aspeed_soc_properties[] = {
- DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = aspeed_soc_realize;
- /* Reason: Uses serial_hds and nd_table in realize() directly */
- dc->user_creatable = false;
- device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
- .name = TYPE_ASPEED_SOC,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(AspeedSoCState),
- .class_size = sizeof(AspeedSoCClass),
- .class_init = aspeed_soc_class_init,
- .abstract = true,
-};
-
-static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-{
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-
- sc->name = "ast2400-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
- sc->silicon_rev = AST2400_A1_SILICON_REV;
- sc->sram_size = 0x8000;
- sc->spis_num = 1;
- sc->ehcis_num = 1;
- sc->wdts_num = 2;
- sc->macs_num = 2;
- sc->uarts_num = 5;
- sc->irqmap = aspeed_soc_ast2400_irqmap;
- sc->memmap = aspeed_soc_ast2400_memmap;
- sc->num_cpus = 1;
- sc->get_irq = aspeed_soc_ast2400_get_irq;
-}
-
-static const TypeInfo aspeed_soc_ast2400_type_info = {
- .name = "ast2400-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_soc_init,
- .instance_size = sizeof(AspeedSoCState),
- .class_init = aspeed_soc_ast2400_class_init,
-};
-
-static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
-{
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-
- sc->name = "ast2500-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
- sc->silicon_rev = AST2500_A1_SILICON_REV;
- sc->sram_size = 0x9000;
- sc->spis_num = 2;
- sc->ehcis_num = 2;
- sc->wdts_num = 3;
- sc->macs_num = 2;
- sc->uarts_num = 5;
- sc->irqmap = aspeed_soc_ast2500_irqmap;
- sc->memmap = aspeed_soc_ast2500_memmap;
- sc->num_cpus = 1;
- sc->get_irq = aspeed_soc_ast2400_get_irq;
-}
-
-static const TypeInfo aspeed_soc_ast2500_type_info = {
- .name = "ast2500-a1",
- .parent = TYPE_ASPEED_SOC,
- .instance_init = aspeed_soc_init,
- .instance_size = sizeof(AspeedSoCState),
- .class_init = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
- type_register_static(&aspeed_soc_type_info);
- type_register_static(&aspeed_soc_ast2400_type_info);
- type_register_static(&aspeed_soc_ast2500_type_info);
-};
-
-type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
- return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- SerialMM *smm;
-
- for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
- smm = &s->uart[i];
-
- /* Chardev property is set by the machine. */
- qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
- qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
- qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
- qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
- if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
- return false;
- }
-
- sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
- aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
- }
-
- return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- int i = dev - ASPEED_DEV_UART1;
-
- g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
- qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- ram_addr_t ram_size, max_ram_size;
-
- ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
- &error_abort);
- max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
- &error_abort);
-
- memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
- max_ram_size);
- memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
- /*
- * Add a memory region beyond the RAM region to let firmwares scan
- * the address space with load/store and guess how much RAM the
- * SoC has.
- */
- if (ram_size < max_ram_size) {
- DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
- qdev_prop_set_string(dev, "name", "ram-empty");
- qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
- if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
- return false;
- }
-
- memory_region_add_subregion_overlap(&s->dram_container, ram_size,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
- }
-
- memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
- return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
- memory_region_add_subregion(s->memory, addr,
- sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
- const char *name, hwaddr addr, uint64_t size)
-{
- qdev_prop_set_string(DEVICE(dev), "name", name);
- qdev_prop_set_uint64(DEVICE(dev), "size", size);
- sysbus_realize(dev, &error_abort);
-
- memory_region_add_subregion_overlap(s->memory, addr,
- sysbus_mmio_get_region(dev, 0), -1000);
-}
--- /dev/null
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+ return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ SerialMM *smm;
+
+ for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+ smm = &s->uart[i];
+
+ /* Chardev property is set by the machine. */
+ qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+ qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+ qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+ return false;
+ }
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+ }
+
+ return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i = dev - ASPEED_DEV_UART1;
+
+ g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ ram_addr_t ram_size, max_ram_size;
+
+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+ &error_abort);
+ max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+ &error_abort);
+
+ memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+ max_ram_size);
+ memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+ /*
+ * Add a memory region beyond the RAM region to let firmwares scan
+ * the address space with load/store and guess how much RAM the
+ * SoC has.
+ */
+ if (ram_size < max_ram_size) {
+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+ qdev_prop_set_string(dev, "name", "ram-empty");
+ qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+ return false;
+ }
+
+ memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+ }
+
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+ return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+ memory_region_add_subregion(s->memory, addr,
+ sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+ const char *name, hwaddr addr, uint64_t size)
+{
+ qdev_prop_set_string(DEVICE(dev), "name", name);
+ qdev_prop_set_uint64(DEVICE(dev), "size", size);
+ sysbus_realize(dev, &error_abort);
+
+ memory_region_add_subregion_overlap(s->memory, addr,
+ sysbus_mmio_get_region(dev, 0), -1000);
+}
+
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSoCState *s = ASPEED_SOC(dev);
+
+ if (!s->memory) {
+ error_setg(errp, "'memory' link is not set");
+ return;
+ }
+}
+
+static Property aspeed_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_soc_realize;
+ device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+ {
+ .name = TYPE_ASPEED_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AspeedSoCState),
+ .class_size = sizeof(AspeedSoCClass),
+ .class_init = aspeed_soc_class_init,
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
MemoryRegion bic_memory;
Clock *bic_sysclk;
- AspeedSoCState bmc;
- AspeedSoCState bic;
+ Aspeed2600SoCState bmc;
+ Aspeed10x0SoCState bic;
bool mmio_exec;
};
static void fby35_bmc_init(Fby35State *s)
{
+ AspeedSoCState *soc;
+
object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+ soc = ASPEED_SOC(&s->bmc);
memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
UINT64_MAX);
&error_abort);
object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
&error_abort);
- aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
- aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+ aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
/* Install first FMC flash content as a boot rom. */
if (!s->mmio_exec) {
DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
if (mtd0) {
- AspeedSoCState *bmc = &s->bmc;
- uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+ uint64_t rom_size = memory_region_size(&soc->spi_boot);
memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
rom_size, &error_abort);
- memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+ memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
&s->bmc_boot_rom, 1);
fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
static void fby35_bic_init(Fby35State *s)
{
+ AspeedSoCState *soc;
+
s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
clock_set_hz(s->bic_sysclk, 200000000ULL);
object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+ soc = ASPEED_SOC(&s->bic);
memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
UINT64_MAX);
qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
&error_abort);
- aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
- aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
- aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
- aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+ aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+ aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+ aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
}
static void fby35_init(MachineState *machine)
arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
- 'aspeed_soc.c',
'aspeed.c',
+ 'aspeed_soc_common.c',
+ 'aspeed_ast2400.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
#define ASPEED_JTAG_NUM 2
struct AspeedSoCState {
- /*< private >*/
DeviceState parent;
- /*< public >*/
- ARMCPU cpu[ASPEED_CPUS_NUM];
- A15MPPrivState a7mpcore;
- ARMv7MState armv7m;
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
- AspeedVICState vic;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
#define TYPE_ASPEED_SOC "aspeed-soc"
OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
+struct Aspeed2400SoCState {
+ AspeedSoCState parent;
+
+ ARMCPU cpu[ASPEED_CPUS_NUM];
+ AspeedVICState vic;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
+struct Aspeed2600SoCState {
+ AspeedSoCState parent;
+
+ A15MPPrivState a7mpcore;
+ ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
+struct Aspeed10x0SoCState {
+ AspeedSoCState parent;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
struct AspeedSoCClass {
DeviceClass parent_class;
projects / mirror_qemu.git / commitdiff