/**
* MIPSCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A MIPS CPU model.
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} MIPSCPUClass;
cpu_state_reset(env);
}
+static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ MIPSCPU *cpu = MIPS_CPU(dev);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
+
+ cpu_reset(CPU(cpu));
+ qemu_init_vcpu(&cpu->env);
+
+ mcc->parent_realize(dev, errp);
+}
+
static void mips_cpu_initfn(Object *obj)
{
MIPSCPU *cpu = MIPS_CPU(obj);
{
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
+ DeviceClass *dc = DEVICE_CLASS(c);
+
+ mcc->parent_realize = dc->realize;
+ dc->realize = mips_cpu_realizefn;
mcc->parent_reset = cc->reset;
cc->reset = mips_cpu_reset;