e1000e: Set HW FIFO minimum pointer gap for non-gig speeds

Based on feedback from HW team, the configured value of the internal PHY
HW FIFO pointer gap was incorrect for non-gig speeds.
This patch provides the correct configuration.

Signed-off-by: Raanan Avargil <raanan.avargil@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index 786d2148dd673d986513f6b9baae603dadf379d7..e7ccf5ffa835bc98f9c79c6fa583087ba52d361b 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1479,6 +1479,18 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                                hw->phy.ops.release(hw);
                                if (ret_val)
                                        return ret_val;
+                       } else {
+                               ret_val = hw->phy.ops.acquire(hw);
+                               if (ret_val)
+                                       return ret_val;
+
+                               ret_val = e1e_wphy_locked(hw,
+                                                         PHY_REG(776, 20),
+                                                         0xC023);
+                               hw->phy.ops.release(hw);
+                               if (ret_val)
+                                       return ret_val;
+
                        }
                }
        }