ARM: dts/imx6q-bx50v3: Set display interface clock parents

BugLink: https://bugs.launchpad.net/bugs/1881927
[ Upstream commit 665e7c73a7724a393b4ec92d1ae1e029925ef2b7 ]

Avoid LDB and IPU DI clocks both using the same parent. LDB requires
pasthrough clock to avoid breaking timing while IPU DI does not.

Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.

This fixes an issue where attempting atomic modeset while using
HDMI and display port at the same time causes LDB clock programming
to destroy the programming of HDMI that was done during the same
modeset.

Cc: stable@vger.kernel.org
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
[Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
 originally chosen by Robert Beckett to avoid affecting eMMC clock
 by DRM atomic updates]
Signed-off-by: Ian Ray <ian.ray@ge.com>
[Squash Robert's and Ian's commits for bisectability, update patch
 description and add stable tag]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index 95b8f2d7182144ba90d6fa0cce12712e42add476..fb0980190aa07e84499180e99d42580b9ca0805a 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -65,13 +65,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
 &ldb {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index 611cb7ae7e556ec761af31bd7739c589d0405eac..8f762d9c5ae9962f68cce12c5b75938eca1716c4 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -65,13 +65,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
 &ldb {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index e4cb118f88c6c4c7854a176be6ba9dc929ff3d79..1ea64ecf4291c4d661a4ed22b963a351de10585b 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -53,17 +53,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
-                         <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
-                         <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-                                <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
 &ldb {
        fsl,dual-channel;
        status = "okay";

diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index fa27dcdf06f1b3284f6d19812f48ee6f7cd4087b..1938b04199c484892153b9f0d7705935e5464bb1 100644 (file)
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -377,3 +377,18 @@
                #interrupt-cells = <1>;
        };
 };
+
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+                         <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};