clk: sunxi-ng: r40: rewrite init code to a platform driver

As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.

Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42aa9dabc3e8b541b6543eb8fdd2828..c3aa839a453de8325e1b63cab5bf02cdb95ffbff 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -12,7 +12,8 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #include "ccu_common.h"
 #include "ccu_reset.h"
@@ -1250,17 +1251,17 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
        .bypass_index   = 1, /* index of 24 MHz oscillator */
 };
 
-static void __init sun8i_r40_ccu_setup(struct device_node *node)
+static int sun8i_r40_ccu_probe(struct platform_device *pdev)
 {
+       struct resource *res;
        void __iomem *reg;
        u32 val;
+       int ret;
 
-       reg = of_io_request_and_map(node, 0, of_node_full_name(node));
-       if (IS_ERR(reg)) {
-               pr_err("%s: Could not map the clock registers\n",
-                      of_node_full_name(node));
-               return;
-       }
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       reg = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(reg))
+               return PTR_ERR(reg);
 
        /* Force the PLL-Audio-1x divider to 4 */
        val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
@@ -1277,7 +1278,9 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
        val &= ~GENMASK(25, 20);
        writel(val, reg + SUN8I_R40_USB_CLK_REG);
 
-       sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
+       ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
+       if (ret)
+               return ret;
 
        /* Gate then ungate PLL CPU after any rate changes */
        ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
@@ -1285,6 +1288,20 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
        /* Reparent CPU during PLL CPU rate changes */
        ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
                                  &sun8i_r40_cpu_nb);
+
+       return 0;
 }
-CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
-              sun8i_r40_ccu_setup);
+
+static const struct of_device_id sun8i_r40_ccu_ids[] = {
+       { .compatible = "allwinner,sun8i-r40-ccu" },
+       { }
+};
+
+static struct platform_driver sun8i_r40_ccu_driver = {
+       .probe  = sun8i_r40_ccu_probe,
+       .driver = {
+               .name   = "sun8i-r40-ccu",
+               .of_match_table = sun8i_r40_ccu_ids,
+       },
+};
+builtin_platform_driver(sun8i_r40_ccu_driver);