return ret;
}
+static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
+ ppcmas_tlb_t *tlb)
+{
+ uint8_t i;
+ int32_t tsize = -1;
+
+ for (i = 0; i < 32; i++) {
+ if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
+ if (tsize == -1) {
+ tsize = i;
+ } else {
+ return;
+ }
+ }
+ }
+
+ /* TLBnPS unimplemented? Odd.. */
+ assert(tsize != -1);
+ tlb->mas1 &= ~MAS1_TSIZE_MASK;
+ tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
+}
+
#endif
static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
env->spr[SPR_BOOKE_MAS3];
tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
- /* MAV 1.0 only */
- if (!(tlbncfg & TLBnCFG_AVAIL)) {
- /* force !AVAIL TLB entries to correct page size */
- tlb->mas1 &= ~MAS1_TSIZE_MASK;
- /* XXX can be configured in MMUCSR0 */
- tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+ if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+ /* For TLB which has a fixed size TSIZE is ignored with MAV2 */
+ booke206_fixed_size_tlbn(env, tlbn, tlb);
+ } else {
+ if (!(tlbncfg & TLBnCFG_AVAIL)) {
+ /* force !AVAIL TLB entries to correct page size */
+ tlb->mas1 &= ~MAS1_TSIZE_MASK;
+ /* XXX can be configured in MMUCSR0 */
+ tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+ }
}
/* Make a mask from TLB size to discard invalid bits in EPN field */