common-obj-y += bt.o bt-host.o bt-vhci.o bt-l2cap.o bt-sdp.o bt-hci.o bt-hid.o usb-bt.o
common-obj-y += bt-hci-csr.o
common-obj-y += buffered_file.o migration.o migration-tcp.o
-common-obj-y += qemu-char.o savevm.o #aio.o
+common-obj-y += qemu-char.o #aio.o
common-obj-y += msmouse.o ps2.o
common-obj-y += qdev.o qdev-properties.o
common-obj-y += block-migration.o iohandler.o
obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
-obj-y += memory.o
+obj-y += memory.o savevm.o
LIBS+=-lz
QEMU_CFLAGS += $(VNC_TLS_CFLAGS)
{
RAMBlock *block = last_block;
ram_addr_t offset = last_offset;
- ram_addr_t current_addr;
int bytes_sent = 0;
+ MemoryRegion *mr;
if (!block)
block = QLIST_FIRST(&ram_list.blocks);
- current_addr = block->offset + offset;
-
do {
- if (cpu_physical_memory_get_dirty(current_addr, MIGRATION_DIRTY_FLAG)) {
+ mr = block->mr;
+ if (memory_region_get_dirty(mr, offset, DIRTY_MEMORY_MIGRATION)) {
uint8_t *p;
int cont = (block == last_block) ? RAM_SAVE_FLAG_CONTINUE : 0;
- cpu_physical_memory_reset_dirty(current_addr,
- current_addr + TARGET_PAGE_SIZE,
- MIGRATION_DIRTY_FLAG);
+ memory_region_reset_dirty(mr, offset, TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_MIGRATION);
- p = block->host + offset;
+ p = memory_region_get_ram_ptr(mr) + offset;
if (is_dup_page(p, *p)) {
qemu_put_be64(f, offset | cont | RAM_SAVE_FLAG_COMPRESS);
if (!block)
block = QLIST_FIRST(&ram_list.blocks);
}
-
- current_addr = block->offset + offset;
-
- } while (current_addr != last_block->offset + last_offset);
+ } while (block != last_block || offset != last_offset);
last_block = block;
last_offset = offset;
QLIST_FOREACH(block, &ram_list.blocks, next) {
ram_addr_t addr;
- for (addr = block->offset; addr < block->offset + block->length;
- addr += TARGET_PAGE_SIZE) {
- if (cpu_physical_memory_get_dirty(addr, MIGRATION_DIRTY_FLAG)) {
+ for (addr = 0; addr < block->length; addr += TARGET_PAGE_SIZE) {
+ if (memory_region_get_dirty(block->mr, addr,
+ DIRTY_MEMORY_MIGRATION)) {
count++;
}
}
{
RAMBlock * const *ablock = a;
RAMBlock * const *bblock = b;
- if ((*ablock)->offset < (*bblock)->offset) {
- return -1;
- } else if ((*ablock)->offset > (*bblock)->offset) {
- return 1;
- }
- return 0;
+
+ return strcmp((*ablock)->idstr, (*bblock)->idstr);
}
static void sort_ram_list(void)
int ret;
if (stage < 0) {
- cpu_physical_memory_set_dirty_tracking(0);
+ memory_global_dirty_log_stop();
return 0;
}
/* Make sure all dirty bits are set */
QLIST_FOREACH(block, &ram_list.blocks, next) {
- for (addr = block->offset; addr < block->offset + block->length;
- addr += TARGET_PAGE_SIZE) {
- if (!cpu_physical_memory_get_dirty(addr,
- MIGRATION_DIRTY_FLAG)) {
- cpu_physical_memory_set_dirty(addr);
+ for (addr = 0; addr < block->length; addr += TARGET_PAGE_SIZE) {
+ if (!memory_region_get_dirty(block->mr, addr,
+ DIRTY_MEMORY_MIGRATION)) {
+ memory_region_set_dirty(block->mr, addr);
}
}
}
- /* Enable dirty memory tracking */
- cpu_physical_memory_set_dirty_tracking(1);
+ memory_global_dirty_log_start();
qemu_put_be64(f, ram_bytes_total() | RAM_SAVE_FLAG_MEM_SIZE);
while ((bytes_sent = ram_save_block(f)) != 0) {
bytes_transferred += bytes_sent;
}
- cpu_physical_memory_set_dirty_tracking(0);
+ memory_global_dirty_log_stop();
}
qemu_put_be64(f, RAM_SAVE_FLAG_EOS);
return NULL;
}
- return block->host + offset;
+ return memory_region_get_ram_ptr(block->mr) + offset;
}
len = qemu_get_byte(f);
QLIST_FOREACH(block, &ram_list.blocks, next) {
if (!strncmp(id, block->idstr, sizeof(id)))
- return block->host + offset;
+ return memory_region_get_ram_ptr(block->mr) + offset;
}
fprintf(stderr, "Can't find block %s!\n", id);
int flags;
int error;
- if (version_id < 3 || version_id > 4) {
+ if (version_id < 4 || version_id > 4) {
return -EINVAL;
}
addr &= TARGET_PAGE_MASK;
if (flags & RAM_SAVE_FLAG_MEM_SIZE) {
- if (version_id == 3) {
- if (addr != ram_bytes_total()) {
- return -EINVAL;
- }
- } else {
+ if (version_id == 4) {
/* Synchronize RAM block list */
char id[256];
ram_addr_t length;
void *host;
uint8_t ch;
- if (version_id == 3)
- host = qemu_get_ram_ptr(addr);
- else
- host = host_from_stream_offset(f, addr, flags);
+ host = host_from_stream_offset(f, addr, flags);
if (!host) {
return -EINVAL;
}
} else if (flags & RAM_SAVE_FLAG_PAGE) {
void *host;
- if (version_id == 3)
- host = qemu_get_ram_ptr(addr);
- else
- host = host_from_stream_offset(f, addr, flags);
+ host = host_from_stream_offset(f, addr, flags);
qemu_get_buffer(f, host, TARGET_PAGE_SIZE);
}
#define RAM_PREALLOC_MASK (1 << 0)
typedef struct RAMBlock {
+ struct MemoryRegion *mr;
uint8_t *host;
ram_addr_t offset;
ram_addr_t length;
3 flags. The ROMD code stores the page ram offset in iotlb entry,
so only a limited number of ids are avaiable. */
-#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
+#define IO_MEM_NB_ENTRIES (1 << TARGET_PAGE_BITS)
/* Flags stored in the low bits of the TLB virtual address. These are
defined so that fast path ram access is all zeros. */
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << 5)
-#define VGA_DIRTY_FLAG 0x01
-#define CODE_DIRTY_FLAG 0x02
-#define MIGRATION_DIRTY_FLAG 0x08
-
-/* read dirty bit (return 0 or 1) */
-static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
-{
- return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
-}
-
-static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr)
-{
- return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS];
-}
-
-static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
- int dirty_flags)
-{
- return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
-}
-
-static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
-{
- ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
-}
-
-static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr,
- int dirty_flags)
-{
- return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags;
-}
-
-static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start,
- int length,
- int dirty_flags)
-{
- int i, mask, len;
- uint8_t *p;
-
- len = length >> TARGET_PAGE_BITS;
- mask = ~dirty_flags;
- p = ram_list.phys_dirty + (start >> TARGET_PAGE_BITS);
- for (i = 0; i < len; i++) {
- p[i] &= mask;
- }
-}
-
-void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
- int dirty_flags);
void cpu_tlb_update_dirty(CPUState *env);
-int cpu_physical_memory_set_dirty_tracking(int enable);
-
-int cpu_physical_memory_get_dirty_tracking(void);
-
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */
/* This should not be used by devices. */
int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
+void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write);
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len);
-#define IO_MEM_SHIFT 3
-
-#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
-#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
-#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
-#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
-#define IO_MEM_SUBPAGE_RAM (4 << IO_MEM_SHIFT)
-
-/* Acts like a ROM when read and like a device when written. */
-#define IO_MEM_ROMD (1)
-#define IO_MEM_SUBPAGE (2)
+extern struct MemoryRegion io_mem_ram;
+extern struct MemoryRegion io_mem_rom;
+extern struct MemoryRegion io_mem_unassigned;
+extern struct MemoryRegion io_mem_notdirty;
#endif
#if !defined(CONFIG_USER_ONLY)
-extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
-extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
-extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
+uint64_t io_mem_read(int index, target_phys_addr_t addr, unsigned size);
+void io_mem_write(int index, target_phys_addr_t addr, uint64_t value,
+ unsigned size);
+extern struct MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr);
return addr;
}
#else
-/* NOTE: this function can trigger an exception */
-/* NOTE2: the returned address is not exactly the physical address: it
- is the offset relative to phys_ram_base */
-static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
-{
- int mmu_idx, page_index, pd;
- void *p;
-
- page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- mmu_idx = cpu_mmu_index(env1);
- if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
- (addr & TARGET_PAGE_MASK))) {
- ldub_code(addr);
- }
- pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
- if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
- cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
-#else
- cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
-#endif
- }
- p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
- return qemu_ram_addr_from_host_nofail(p);
-}
+tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr);
#endif
typedef void (CPUDebugExcpHandler)(CPUState *env);
#ifndef CONFIG_USER_ONLY
-ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
- ram_addr_t size, void *host,
+ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
MemoryRegion *mr);
-ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size,
- MemoryRegion *mr);
+ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr);
void qemu_ram_free(ram_addr_t addr);
void qemu_ram_free_from_ptr(ram_addr_t addr);
-int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
- CPUWriteMemoryFunc * const *mem_write,
- void *opaque, enum device_endian endian);
+struct MemoryRegion;
+int cpu_register_io_memory(MemoryRegion *mr);
void cpu_unregister_io_memory(int table_address);
-void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset,
- ram_addr_t region_offset,
- bool log_dirty);
+struct MemoryRegionSection;
+void cpu_register_physical_memory_log(struct MemoryRegionSection *section,
+ bool readable, bool readonly);
-static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset,
- ram_addr_t region_offset)
+void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+
+int cpu_physical_memory_set_dirty_tracking(int enable);
+
+#define VGA_DIRTY_FLAG 0x01
+#define CODE_DIRTY_FLAG 0x02
+#define MIGRATION_DIRTY_FLAG 0x08
+
+/* read dirty bit (return 0 or 1) */
+static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
{
- cpu_register_physical_memory_log(start_addr, size, phys_offset,
- region_offset, false);
+ return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
-static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset)
+static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr)
{
- cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
+ return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS];
}
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
+ int dirty_flags)
+{
+ return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
+}
+
+static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
+{
+ ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
+}
+
+static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr,
+ int dirty_flags)
+{
+ return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags;
+}
+
+static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start,
+ int length,
+ int dirty_flags)
+{
+ int i, mask, len;
+ uint8_t *p;
+
+ len = length >> TARGET_PAGE_BITS;
+ mask = ~dirty_flags;
+ p = ram_list.phys_dirty + (start >> TARGET_PAGE_BITS);
+ for (i = 0; i < len; i++) {
+ p[i] &= mask;
+ }
+}
+void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
+ int dirty_flags);
#endif
#endif
static MemoryRegion *system_memory;
static MemoryRegion *system_io;
+MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty;
+static MemoryRegion io_mem_subpage_ram;
+
#endif
CPUState *first_cpu;
static void memory_map_init(void);
/* io memory support */
-CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
-CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
-void *io_mem_opaque[IO_MEM_NB_ENTRIES];
+MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
static char io_mem_used[IO_MEM_NB_ENTRIES];
-static int io_mem_watch;
+static MemoryRegion io_mem_watch;
#endif
/* log support */
*lp = pd = g_malloc(sizeof(PhysPageDesc) * L2_SIZE);
for (i = 0; i < L2_SIZE; i++) {
- pd[i].phys_offset = IO_MEM_UNASSIGNED;
+ pd[i].phys_offset = io_mem_unassigned.ram_addr;
pd[i].region_offset = (first_index + i) << TARGET_PAGE_BITS;
}
}
return pd + (index & (L2_SIZE - 1));
}
-static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
+static inline PhysPageDesc phys_page_find(target_phys_addr_t index)
{
- return phys_page_find_alloc(index, 0);
+ PhysPageDesc *p = phys_page_find_alloc(index, 0);
+
+ if (p) {
+ return *p;
+ } else {
+ return (PhysPageDesc) {
+ .phys_offset = io_mem_unassigned.ram_addr,
+ .region_offset = index << TARGET_PAGE_BITS,
+ };
+ }
}
static void tlb_protect_code(ram_addr_t ram_addr);
target_phys_addr_t addr;
target_ulong pd;
ram_addr_t ram_addr;
- PhysPageDesc *p;
+ PhysPageDesc p;
addr = cpu_get_phys_page_debug(env, pc);
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
}
unsigned long start, unsigned long length)
{
unsigned long addr;
- if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
+ if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
if ((addr - start) < length) {
tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
{
int ret = 0;
in_migration = enable;
- if (enable) {
- memory_global_dirty_log_start();
- } else {
- memory_global_dirty_log_stop();
- }
return ret;
}
-int cpu_physical_memory_get_dirty_tracking(void)
-{
- return in_migration;
-}
-
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
{
ram_addr_t ram_addr;
void *p;
- if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
+ if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK)
+ tlb_entry->addend);
ram_addr = qemu_ram_addr_from_host_nofail(p);
env->tlb_flush_mask = mask;
}
+static bool is_ram_rom(ram_addr_t pd)
+{
+ pd &= ~TARGET_PAGE_MASK;
+ return pd == io_mem_ram.ram_addr || pd == io_mem_rom.ram_addr;
+}
+
+static bool is_romd(ram_addr_t pd)
+{
+ MemoryRegion *mr;
+
+ pd &= ~TARGET_PAGE_MASK;
+ mr = io_mem_region[pd];
+ return mr->rom_device && mr->readable;
+}
+
+static bool is_ram_rom_romd(ram_addr_t pd)
+{
+ return is_ram_rom(pd) || is_romd(pd);
+}
+
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
target_phys_addr_t paddr, int prot,
int mmu_idx, target_ulong size)
{
- PhysPageDesc *p;
+ PhysPageDesc p;
unsigned long pd;
unsigned int index;
target_ulong address;
tlb_add_large_page(env, vaddr, size);
}
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
#if defined(DEBUG_TLB)
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
" prot=%x idx=%d pd=0x%08lx\n",
#endif
address = vaddr;
- if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
+ if (!is_ram_rom_romd(pd)) {
/* IO memory case (romd handled later) */
address |= TLB_MMIO;
}
addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
- if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
+ if (is_ram_rom(pd)) {
/* Normal RAM. */
iotlb = pd & TARGET_PAGE_MASK;
- if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
- iotlb |= IO_MEM_NOTDIRTY;
+ if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr)
+ iotlb |= io_mem_notdirty.ram_addr;
else
- iotlb |= IO_MEM_ROM;
+ iotlb |= io_mem_rom.ram_addr;
} else {
/* IO handlers are currently passed a physical address.
It would be nice to pass an offset from the base address
We can't use the high bits of pd for this because
IO_MEM_ROMD uses these as a ram address. */
iotlb = (pd & ~TARGET_PAGE_MASK);
- if (p) {
- iotlb += p->region_offset;
- } else {
- iotlb += paddr;
- }
+ iotlb += p.region_offset;
}
code_address = address;
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
/* Avoid trapping reads of pages with a write breakpoint. */
if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
- iotlb = io_mem_watch + paddr;
+ iotlb = io_mem_watch.ram_addr + paddr;
address |= TLB_MMIO;
break;
}
te->addr_code = -1;
}
if (prot & PAGE_WRITE) {
- if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
- (pd & IO_MEM_ROMD)) {
+ if ((pd & ~TARGET_PAGE_MASK) == io_mem_rom.ram_addr || is_romd(pd)) {
/* Write access calls the I/O callback. */
te->addr_write = address | TLB_MMIO;
- } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
+ } else if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr &&
!cpu_physical_memory_is_dirty(pd)) {
te->addr_write = address | TLB_NOTDIRTY;
} else {
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
+ MemoryRegion iomem;
target_phys_addr_t base;
ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
ram_addr_t region_offset[TARGET_PAGE_SIZE];
start_addr and region_offset are rounded down to a page boundary
before calculating this offset. This should not be a problem unless
the low bits of start_addr and region_offset differ. */
-void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
- ram_addr_t size,
- ram_addr_t phys_offset,
- ram_addr_t region_offset,
- bool log_dirty)
+void cpu_register_physical_memory_log(MemoryRegionSection *section,
+ bool readable, bool readonly)
{
+ target_phys_addr_t start_addr = section->offset_within_address_space;
+ ram_addr_t size = section->size;
+ ram_addr_t phys_offset = section->mr->ram_addr;
+ ram_addr_t region_offset = section->offset_within_region;
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
ram_addr_t orig_size = size;
subpage_t *subpage;
+ if (memory_region_is_ram(section->mr)) {
+ phys_offset += region_offset;
+ region_offset = 0;
+ }
+
+ if (readonly) {
+ phys_offset |= io_mem_rom.ram_addr;
+ }
+
assert(size);
- if (phys_offset == IO_MEM_UNASSIGNED) {
+ if (phys_offset == io_mem_unassigned.ram_addr) {
region_offset = start_addr;
}
region_offset &= TARGET_PAGE_MASK;
addr = start_addr;
do {
- p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
+ p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 0);
+ if (p && p->phys_offset != io_mem_unassigned.ram_addr) {
ram_addr_t orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
+ MemoryRegion *mr = io_mem_region[orig_memory & ~TARGET_PAGE_MASK];
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
need_subpage);
if (need_subpage) {
- if (!(orig_memory & IO_MEM_SUBPAGE)) {
+ if (!(mr->subpage)) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
&p->phys_offset, orig_memory,
p->region_offset);
} else {
- subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
- >> IO_MEM_SHIFT];
+ subpage = container_of(mr, subpage_t, iomem);
}
subpage_register(subpage, start_addr2, end_addr2, phys_offset,
region_offset);
p->region_offset = 0;
} else {
p->phys_offset = phys_offset;
- if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
- (phys_offset & IO_MEM_ROMD))
+ p->region_offset = region_offset;
+ if (is_ram_rom_romd(phys_offset))
phys_offset += TARGET_PAGE_SIZE;
}
} else {
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
p->phys_offset = phys_offset;
p->region_offset = region_offset;
- if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
- (phys_offset & IO_MEM_ROMD)) {
+ if (is_ram_rom_romd(phys_offset)) {
phys_offset += TARGET_PAGE_SIZE;
} else {
target_phys_addr_t start_addr2, end_addr2;
if (need_subpage) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
- &p->phys_offset, IO_MEM_UNASSIGNED,
+ &p->phys_offset,
+ io_mem_unassigned.ram_addr,
addr & TARGET_PAGE_MASK);
subpage_register(subpage, start_addr2, end_addr2,
phys_offset, region_offset);
return last;
}
-ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
- ram_addr_t size, void *host,
- MemoryRegion *mr)
+void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
{
RAMBlock *new_block, *block;
- size = TARGET_PAGE_ALIGN(size);
- new_block = g_malloc0(sizeof(*new_block));
+ new_block = NULL;
+ QLIST_FOREACH(block, &ram_list.blocks, next) {
+ if (block->offset == addr) {
+ new_block = block;
+ break;
+ }
+ }
+ assert(new_block);
+ assert(!new_block->idstr[0]);
if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
char *id = dev->parent_bus->info->get_dev_path(dev);
pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
QLIST_FOREACH(block, &ram_list.blocks, next) {
- if (!strcmp(block->idstr, new_block->idstr)) {
+ if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
new_block->idstr);
abort();
}
}
+}
+
+ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
+ MemoryRegion *mr)
+{
+ RAMBlock *new_block;
+
+ size = TARGET_PAGE_ALIGN(size);
+ new_block = g_malloc0(sizeof(*new_block));
+ new_block->mr = mr;
new_block->offset = find_ram_offset(size);
if (host) {
new_block->host = host;
return new_block->offset;
}
-ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size,
- MemoryRegion *mr)
+ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr)
{
- return qemu_ram_alloc_from_ptr(dev, name, size, NULL, mr);
+ return qemu_ram_alloc_from_ptr(size, NULL, mr);
}
void qemu_ram_free_from_ptr(ram_addr_t addr)
return ram_addr;
}
-static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 1);
+ cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
#endif
return 0;
}
-static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
+static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
+ printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 2);
+ cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
#endif
- return 0;
}
-static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
-{
-#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
-#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 4);
-#endif
- return 0;
-}
-
-static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
-#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 1);
-#endif
-}
+static const MemoryRegionOps unassigned_mem_ops = {
+ .read = unassigned_mem_read,
+ .write = unassigned_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
-static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
-#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 2);
-#endif
+ abort();
}
-static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void error_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
-#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
-#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 4);
-#endif
+ abort();
}
-static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
- unassigned_mem_readb,
- unassigned_mem_readw,
- unassigned_mem_readl,
+static const MemoryRegionOps error_mem_ops = {
+ .read = error_mem_read,
+ .write = error_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
- unassigned_mem_writeb,
- unassigned_mem_writew,
- unassigned_mem_writel,
+static const MemoryRegionOps rom_mem_ops = {
+ .read = error_mem_read,
+ .write = unassigned_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
- uint32_t val)
+static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
+ uint64_t val, unsigned size)
{
int dirty_flags;
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
#if !defined(CONFIG_USER_ONLY)
- tb_invalidate_phys_page_fast(ram_addr, 1);
+ tb_invalidate_phys_page_fast(ram_addr, size);
dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
#endif
}
- stb_p(qemu_get_ram_ptr(ram_addr), val);
- dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
- cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
- /* we remove the notdirty callback only if the code has been
- flushed */
- if (dirty_flags == 0xff)
- tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
-}
-
-static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
- uint32_t val)
-{
- int dirty_flags;
- dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
- if (!(dirty_flags & CODE_DIRTY_FLAG)) {
-#if !defined(CONFIG_USER_ONLY)
- tb_invalidate_phys_page_fast(ram_addr, 2);
- dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
-#endif
- }
- stw_p(qemu_get_ram_ptr(ram_addr), val);
- dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
- cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
- /* we remove the notdirty callback only if the code has been
- flushed */
- if (dirty_flags == 0xff)
- tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
-}
-
-static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
- uint32_t val)
-{
- int dirty_flags;
- dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
- if (!(dirty_flags & CODE_DIRTY_FLAG)) {
-#if !defined(CONFIG_USER_ONLY)
- tb_invalidate_phys_page_fast(ram_addr, 4);
- dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
-#endif
+ switch (size) {
+ case 1:
+ stb_p(qemu_get_ram_ptr(ram_addr), val);
+ break;
+ case 2:
+ stw_p(qemu_get_ram_ptr(ram_addr), val);
+ break;
+ case 4:
+ stl_p(qemu_get_ram_ptr(ram_addr), val);
+ break;
+ default:
+ abort();
}
- stl_p(qemu_get_ram_ptr(ram_addr), val);
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
/* we remove the notdirty callback only if the code has been
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static CPUReadMemoryFunc * const error_mem_read[3] = {
- NULL, /* never used */
- NULL, /* never used */
- NULL, /* never used */
-};
-
-static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
- notdirty_mem_writeb,
- notdirty_mem_writew,
- notdirty_mem_writel,
+static const MemoryRegionOps notdirty_mem_ops = {
+ .read = error_mem_read,
+ .write = notdirty_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* Generate a debug exception if a watchpoint has been hit. */
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
-{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
- return ldub_phys(addr);
-}
-
-static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
- return lduw_phys(addr);
-}
-
-static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
-{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
- return ldl_phys(addr);
-}
-
-static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
- stb_phys(addr, val);
-}
-
-static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
- stw_phys(addr, val);
+ check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
+ switch (size) {
+ case 1: return ldub_phys(addr);
+ case 2: return lduw_phys(addr);
+ case 4: return ldl_phys(addr);
+ default: abort();
+ }
}
-static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void watch_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
- stl_phys(addr, val);
+ check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
+ switch (size) {
+ case 1: stb_phys(addr, val);
+ case 2: stw_phys(addr, val);
+ case 4: stl_phys(addr, val);
+ default: abort();
+ }
}
-static CPUReadMemoryFunc * const watch_mem_read[3] = {
- watch_mem_readb,
- watch_mem_readw,
- watch_mem_readl,
-};
-
-static CPUWriteMemoryFunc * const watch_mem_write[3] = {
- watch_mem_writeb,
- watch_mem_writew,
- watch_mem_writel,
+static const MemoryRegionOps watch_mem_ops = {
+ .read = watch_mem_read,
+ .write = watch_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static inline uint32_t subpage_readlen (subpage_t *mmio,
- target_phys_addr_t addr,
- unsigned int len)
+static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
+ subpage_t *mmio = opaque;
unsigned int idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
addr += mmio->region_offset[idx];
idx = mmio->sub_io_index[idx];
- return io_mem_read[idx][len](io_mem_opaque[idx], addr);
+ return io_mem_read(idx, addr, len);
}
-static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
- uint32_t value, unsigned int len)
+static void subpage_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned len)
{
+ subpage_t *mmio = opaque;
unsigned int idx = SUBPAGE_IDX(addr);
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n",
+ printf("%s: subpage %p len %d addr " TARGET_FMT_plx
+ " idx %d value %"PRIx64"\n",
__func__, mmio, len, addr, idx, value);
#endif
addr += mmio->region_offset[idx];
idx = mmio->sub_io_index[idx];
- io_mem_write[idx][len](io_mem_opaque[idx], addr, value);
-}
-
-static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
-{
- return subpage_readlen(opaque, addr, 0);
-}
-
-static void subpage_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- subpage_writelen(opaque, addr, value, 0);
-}
-
-static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
-{
- return subpage_readlen(opaque, addr, 1);
-}
-
-static void subpage_writew (void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- subpage_writelen(opaque, addr, value, 1);
+ io_mem_write(idx, addr, value, len);
}
-static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
-{
- return subpage_readlen(opaque, addr, 2);
-}
-
-static void subpage_writel (void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- subpage_writelen(opaque, addr, value, 2);
-}
-
-static CPUReadMemoryFunc * const subpage_read[] = {
- &subpage_readb,
- &subpage_readw,
- &subpage_readl,
-};
-
-static CPUWriteMemoryFunc * const subpage_write[] = {
- &subpage_writeb,
- &subpage_writew,
- &subpage_writel,
+static const MemoryRegionOps subpage_ops = {
+ .read = subpage_read,
+ .write = subpage_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t subpage_ram_readb(void *opaque, target_phys_addr_t addr)
-{
- ram_addr_t raddr = addr;
- void *ptr = qemu_get_ram_ptr(raddr);
- return ldub_p(ptr);
-}
-
-static void subpage_ram_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- ram_addr_t raddr = addr;
- void *ptr = qemu_get_ram_ptr(raddr);
- stb_p(ptr, value);
-}
-
-static uint32_t subpage_ram_readw(void *opaque, target_phys_addr_t addr)
+static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
ram_addr_t raddr = addr;
void *ptr = qemu_get_ram_ptr(raddr);
- return lduw_p(ptr);
-}
-
-static void subpage_ram_writew(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- ram_addr_t raddr = addr;
- void *ptr = qemu_get_ram_ptr(raddr);
- stw_p(ptr, value);
-}
-
-static uint32_t subpage_ram_readl(void *opaque, target_phys_addr_t addr)
-{
- ram_addr_t raddr = addr;
- void *ptr = qemu_get_ram_ptr(raddr);
- return ldl_p(ptr);
+ switch (size) {
+ case 1: return ldub_p(ptr);
+ case 2: return lduw_p(ptr);
+ case 4: return ldl_p(ptr);
+ default: abort();
+ }
}
-static void subpage_ram_writel(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
ram_addr_t raddr = addr;
void *ptr = qemu_get_ram_ptr(raddr);
- stl_p(ptr, value);
+ switch (size) {
+ case 1: return stb_p(ptr, value);
+ case 2: return stw_p(ptr, value);
+ case 4: return stl_p(ptr, value);
+ default: abort();
+ }
}
-static CPUReadMemoryFunc * const subpage_ram_read[] = {
- &subpage_ram_readb,
- &subpage_ram_readw,
- &subpage_ram_readl,
-};
-
-static CPUWriteMemoryFunc * const subpage_ram_write[] = {
- &subpage_ram_writeb,
- &subpage_ram_writew,
- &subpage_ram_writel,
+static const MemoryRegionOps subpage_ram_ops = {
+ .read = subpage_ram_read,
+ .write = subpage_ram_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
mmio, start, end, idx, eidx, memory);
#endif
- if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
- memory = IO_MEM_SUBPAGE_RAM;
+ if ((memory & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) {
+ memory = io_mem_subpage_ram.ram_addr;
}
- memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ memory &= IO_MEM_NB_ENTRIES - 1;
for (; idx <= eidx; idx++) {
mmio->sub_io_index[idx] = memory;
mmio->region_offset[idx] = region_offset;
mmio = g_malloc0(sizeof(subpage_t));
mmio->base = base;
- subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&mmio->iomem, &subpage_ops, mmio,
+ "subpage", TARGET_PAGE_SIZE);
+ mmio->iomem.subpage = true;
+ subpage_memory = mmio->iomem.ram_addr;
#if defined(DEBUG_SUBPAGE)
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
#endif
- *phys = subpage_memory | IO_MEM_SUBPAGE;
+ *phys = subpage_memory;
subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset);
return mmio;
return -1;
}
-/*
- * Usually, devices operate in little endian mode. There are devices out
- * there that operate in big endian too. Each device gets byte swapped
- * mmio if plugged onto a CPU that does the other endianness.
- *
- * CPU Device swap?
- *
- * little little no
- * little big yes
- * big little yes
- * big big no
- */
-
-typedef struct SwapEndianContainer {
- CPUReadMemoryFunc *read[3];
- CPUWriteMemoryFunc *write[3];
- void *opaque;
-} SwapEndianContainer;
-
-static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- SwapEndianContainer *c = opaque;
- val = c->read[0](c->opaque, addr);
- return val;
-}
-
-static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- SwapEndianContainer *c = opaque;
- val = bswap16(c->read[1](c->opaque, addr));
- return val;
-}
-
-static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- SwapEndianContainer *c = opaque;
- val = bswap32(c->read[2](c->opaque, addr));
- return val;
-}
-
-static CPUReadMemoryFunc * const swapendian_readfn[3]={
- swapendian_mem_readb,
- swapendian_mem_readw,
- swapendian_mem_readl
-};
-
-static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- SwapEndianContainer *c = opaque;
- c->write[0](c->opaque, addr, val);
-}
-
-static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- SwapEndianContainer *c = opaque;
- c->write[1](c->opaque, addr, bswap16(val));
-}
-
-static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- SwapEndianContainer *c = opaque;
- c->write[2](c->opaque, addr, bswap32(val));
-}
-
-static CPUWriteMemoryFunc * const swapendian_writefn[3]={
- swapendian_mem_writeb,
- swapendian_mem_writew,
- swapendian_mem_writel
-};
-
-static void swapendian_init(int io_index)
-{
- SwapEndianContainer *c = g_malloc(sizeof(SwapEndianContainer));
- int i;
-
- /* Swap mmio for big endian targets */
- c->opaque = io_mem_opaque[io_index];
- for (i = 0; i < 3; i++) {
- c->read[i] = io_mem_read[io_index][i];
- c->write[i] = io_mem_write[io_index][i];
-
- io_mem_read[io_index][i] = swapendian_readfn[i];
- io_mem_write[io_index][i] = swapendian_writefn[i];
- }
- io_mem_opaque[io_index] = c;
-}
-
-static void swapendian_del(int io_index)
-{
- if (io_mem_read[io_index][0] == swapendian_readfn[0]) {
- g_free(io_mem_opaque[io_index]);
- }
-}
-
/* mem_read and mem_write are arrays of functions containing the
function to access byte (index 0), word (index 1) and dword (index
2). Functions can be omitted with a NULL function pointer.
modified. If it is zero, a new io zone is allocated. The return
value can be used with cpu_register_physical_memory(). (-1) is
returned if error. */
-static int cpu_register_io_memory_fixed(int io_index,
- CPUReadMemoryFunc * const *mem_read,
- CPUWriteMemoryFunc * const *mem_write,
- void *opaque, enum device_endian endian)
+static int cpu_register_io_memory_fixed(int io_index, MemoryRegion *mr)
{
- int i;
-
if (io_index <= 0) {
io_index = get_free_io_mem_idx();
if (io_index == -1)
return io_index;
} else {
- io_index >>= IO_MEM_SHIFT;
if (io_index >= IO_MEM_NB_ENTRIES)
return -1;
}
- for (i = 0; i < 3; ++i) {
- io_mem_read[io_index][i]
- = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]);
- }
- for (i = 0; i < 3; ++i) {
- io_mem_write[io_index][i]
- = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]);
- }
- io_mem_opaque[io_index] = opaque;
+ io_mem_region[io_index] = mr;
- switch (endian) {
- case DEVICE_BIG_ENDIAN:
-#ifndef TARGET_WORDS_BIGENDIAN
- swapendian_init(io_index);
-#endif
- break;
- case DEVICE_LITTLE_ENDIAN:
-#ifdef TARGET_WORDS_BIGENDIAN
- swapendian_init(io_index);
-#endif
- break;
- case DEVICE_NATIVE_ENDIAN:
- default:
- break;
- }
-
- return (io_index << IO_MEM_SHIFT);
+ return io_index;
}
-int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
- CPUWriteMemoryFunc * const *mem_write,
- void *opaque, enum device_endian endian)
+int cpu_register_io_memory(MemoryRegion *mr)
{
- return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian);
+ return cpu_register_io_memory_fixed(0, mr);
}
-void cpu_unregister_io_memory(int io_table_address)
+void cpu_unregister_io_memory(int io_index)
{
- int i;
- int io_index = io_table_address >> IO_MEM_SHIFT;
-
- swapendian_del(io_index);
-
- for (i=0;i < 3; i++) {
- io_mem_read[io_index][i] = unassigned_mem_read[i];
- io_mem_write[io_index][i] = unassigned_mem_write[i];
- }
- io_mem_opaque[io_index] = NULL;
+ io_mem_region[io_index] = NULL;
io_mem_used[io_index] = 0;
}
{
int i;
- cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read,
- unassigned_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read,
- unassigned_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read,
- notdirty_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_io_memory_fixed(IO_MEM_SUBPAGE_RAM, subpage_ram_read,
- subpage_ram_write, NULL,
- DEVICE_NATIVE_ENDIAN);
+ /* Must be first: */
+ memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX);
+ assert(io_mem_ram.ram_addr == 0);
+ memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX);
+ memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
+ "unassigned", UINT64_MAX);
+ memory_region_init_io(&io_mem_notdirty, ¬dirty_mem_ops, NULL,
+ "notdirty", UINT64_MAX);
+ memory_region_init_io(&io_mem_subpage_ram, &subpage_ram_ops, NULL,
+ "subpage-ram", UINT64_MAX);
for (i=0; i<5; i++)
io_mem_used[i] = 1;
- io_mem_watch = cpu_register_io_memory(watch_mem_read,
- watch_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
+ "watch", UINT64_MAX);
}
static void memory_map_init(void)
uint32_t val;
target_phys_addr_t page;
ram_addr_t pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
if (l > len)
l = len;
p = phys_page_find(page >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
if (is_write) {
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- target_phys_addr_t addr1 = addr;
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
+ target_phys_addr_t addr1;
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr1 & 3) == 0)) {
/* 32 bit write access */
val = ldl_p(buf);
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
+ io_mem_write(io_index, addr1, val, 4);
l = 4;
} else if (l >= 2 && ((addr1 & 1) == 0)) {
/* 16 bit write access */
val = lduw_p(buf);
- io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
+ io_mem_write(io_index, addr1, val, 2);
l = 2;
} else {
/* 8 bit write access */
val = ldub_p(buf);
- io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
+ io_mem_write(io_index, addr1, val, 1);
l = 1;
}
} else {
qemu_put_ram_ptr(ptr);
}
} else {
- if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
- !(pd & IO_MEM_ROMD)) {
- target_phys_addr_t addr1 = addr;
+ if (!is_ram_rom_romd(pd)) {
+ target_phys_addr_t addr1;
/* I/O case */
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
if (l >= 4 && ((addr1 & 3) == 0)) {
/* 32 bit read access */
- val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
+ val = io_mem_read(io_index, addr1, 4);
stl_p(buf, val);
l = 4;
} else if (l >= 2 && ((addr1 & 1) == 0)) {
/* 16 bit read access */
- val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
+ val = io_mem_read(io_index, addr1, 2);
stw_p(buf, val);
l = 2;
} else {
/* 8 bit read access */
- val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
+ val = io_mem_read(io_index, addr1, 1);
stb_p(buf, val);
l = 1;
}
uint8_t *ptr;
target_phys_addr_t page;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
if (l > len)
l = len;
p = phys_page_find(page >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
- (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
- !(pd & IO_MEM_ROMD)) {
+ if (!is_ram_rom_romd(pd)) {
/* do nothing */
} else {
unsigned long addr1;
int l;
target_phys_addr_t page;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
ram_addr_t raddr = RAM_ADDR_MAX;
ram_addr_t rlen;
void *ret;
if (l > len)
l = len;
p = phys_page_find(page >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
if (todo || bounce.buffer) {
break;
}
uint8_t *ptr;
uint32_t val;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
- !(pd & IO_MEM_ROMD)) {
+ if (!is_ram_rom_romd(pd)) {
/* I/O case */
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
- val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
+ val = io_mem_read(io_index, addr, 4);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
uint8_t *ptr;
uint64_t val;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
- !(pd & IO_MEM_ROMD)) {
+ if (!is_ram_rom_romd(pd)) {
/* I/O case */
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
/* XXX This is broken when device endian != cpu endian.
Fix and add "endian" variable check */
#ifdef TARGET_WORDS_BIGENDIAN
- val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
- val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
+ val = io_mem_read(io_index, addr, 4) << 32;
+ val |= io_mem_read(io_index, addr + 4, 4);
#else
- val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
- val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
+ val = io_mem_read(io_index, addr, 4);
+ val |= io_mem_read(io_index, addr + 4, 4) << 32;
#endif
} else {
/* RAM case */
uint8_t *ptr;
uint64_t val;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
- !(pd & IO_MEM_ROMD)) {
+ if (!is_ram_rom_romd(pd)) {
/* I/O case */
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
- val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
+ val = io_mem_read(io_index, addr, 2);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
int io_index;
uint8_t *ptr;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
+ io_mem_write(io_index, addr, val, 4);
} else {
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
ptr = qemu_get_ram_ptr(addr1);
int io_index;
uint8_t *ptr;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
#ifdef TARGET_WORDS_BIGENDIAN
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
+ io_mem_write(io_index, addr, val >> 32, 4);
+ io_mem_write(io_index, addr + 4, (uint32_t)val, 4);
#else
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
+ io_mem_write(io_index, addr, (uint32_t)val, 4);
+ io_mem_write(io_index, addr + 4, val >> 32, 4);
#endif
} else {
ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
int io_index;
uint8_t *ptr;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
val = bswap32(val);
}
#endif
- io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
+ io_mem_write(io_index, addr, val, 4);
} else {
unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
int io_index;
uint8_t *ptr;
unsigned long pd;
- PhysPageDesc *p;
+ PhysPageDesc p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
- if (!p) {
- pd = IO_MEM_UNASSIGNED;
- } else {
- pd = p->phys_offset;
- }
+ pd = p.phys_offset;
- if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
- if (p)
- addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
+ if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
+ io_index = pd & (IO_MEM_NB_ENTRIES - 1);
+ addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
val = bswap16(val);
}
#endif
- io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
+ io_mem_write(io_index, addr, val, 2);
} else {
unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
tcg_dump_info(f, cpu_fprintf);
}
+/* NOTE: this function can trigger an exception */
+/* NOTE2: the returned address is not exactly the physical address: it
+ is the offset relative to phys_ram_base */
+tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
+{
+ int mmu_idx, page_index, pd;
+ void *p;
+
+ page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ mmu_idx = cpu_mmu_index(env1);
+ if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
+ (addr & TARGET_PAGE_MASK))) {
+ ldub_code(addr);
+ }
+ pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
+ if (pd != io_mem_ram.ram_addr && pd != io_mem_rom.ram_addr
+ && !is_romd(pd)) {
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
+ cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
+#else
+ cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
+#endif
+ }
+ p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
+ return qemu_ram_addr_from_host_nofail(p);
+}
+
#define MMUSUFFIX _cmmu
#undef GETPC
#define GETPC() NULL
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
but the address space hole reserved at this point is 8TB. */
- memory_region_init_ram(&s->ram_region, NULL, "ram", ram_size);
+ memory_region_init_ram(&s->ram_region, "ram", ram_size);
+ vmstate_register_ram_global(&s->ram_region);
memory_region_add_subregion(addr_space, 0, &s->ram_region);
/* TIGbus, 0x801.0000.0000, 1GB. */
env->rambar0 = AN5206_RAMBAR_ADDR | 1;
/* DRAM at address zero */
- memory_region_init_ram(ram, NULL, "an5206.ram", ram_size);
+ memory_region_init_ram(ram, "an5206.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Internal SRAM. */
- memory_region_init_ram(sram, NULL, "an5206.sram", 512);
+ memory_region_init_ram(sram, "an5206.sram", 512);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(address_space_mem, AN5206_MBAR_ADDR, env);
#endif
/* Flash programming is done via the SCU, so pretend it is ROM. */
- memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
+ memory_region_init_ram(flash, "armv7m.flash", flash_size);
+ vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, 0, flash);
- memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
+ memory_region_init_ram(sram, "armv7m.sram", sram_size);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, 0x20000000, sram);
armv7m_bitband_init();
/* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */
- memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
+ memory_region_init_ram(hack, "armv7m.hack", 0x1000);
+ vmstate_register_ram_global(hack);
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
qemu_register_reset(armv7m_reset, env);
env = cpu_init(cpu_model);
/* allocate RAM */
- memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
+ memory_region_init_ram(phys_ram, "axisdev88.ram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */
- memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
+ memory_region_init_ram(phys_intmem, "axisdev88.chipram", INTMEM_SIZE);
+ vmstate_register_ram_global(phys_intmem);
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
/* Attach a NAND flash to CS1. */
env->vbr = 0;
/* RAM at address zero */
- memory_region_init_ram(ram, NULL, "dummy_m68k.ram", ram_size);
+ memory_region_init_ram(ram, "dummy_m68k.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Load kernel. */
g364fb_screen_dump, NULL, s);
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
- memory_region_init_ram_ptr(&s->mem_vram, dev, "vram",
+ memory_region_init_ram_ptr(&s->mem_vram, "vram",
s->vram_size, s->vram);
+ vmstate_register_ram(&s->mem_vram, dev);
memory_region_set_coalescing(&s->mem_vram);
}
int required_for_version);
void vmstate_unregister(DeviceState *dev, const VMStateDescription *vmsd,
void *opaque);
+struct MemoryRegion;
+void vmstate_register_ram(struct MemoryRegion *memory, DeviceState *dev);
+void vmstate_unregister_ram(struct MemoryRegion *memory, DeviceState *dev);
+void vmstate_register_ram_global(struct MemoryRegion *memory);
+
#endif
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
- memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
+ memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
+ vmstate_register_ram_global(&s->flash);
s->flash_mapped = false;
memory_region_init_io(&s->iomem, &integratorcm_ops, s,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
+ memory_region_init_ram(ram, "integrator.ram", ram_size);
+ vmstate_register_ram_global(ram);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
- memory_region_init_ram_ptr(&s->ivshmem, &s->dev.qdev, "ivshmem.bar2",
+ memory_region_init_ram_ptr(&s->ivshmem, "ivshmem.bar2",
s->ivshmem_size, ptr);
+ vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
/* mmap the region and map into the BAR2 */
map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED,
incoming_fd, 0);
- memory_region_init_ram_ptr(&s->ivshmem, &s->dev.qdev,
+ memory_region_init_ram_ptr(&s->ivshmem,
"ivshmem.bar2", s->ivshmem_size, map_ptr);
+ vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
IVSHMEM_DPRINTF("guest h/w addr = %" PRIu64 ", size = %" PRIu64 "\n",
s->ivshmem_offset, s->ivshmem_size);
memory_region_destroy(&s->ivshmem_mmio);
memory_region_del_subregion(&s->bar, &s->ivshmem);
+ vmstate_unregister_ram(&s->ivshmem, &s->dev.qdev);
memory_region_destroy(&s->ivshmem);
memory_region_destroy(&s->bar);
unregister_savevm(&dev->qdev, "ivshmem", s);
exit(1);
}
- memory_region_init_ram(ram, NULL, "leon3.ram", ram_size);
+ memory_region_init_ram(ram, "leon3.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */
- memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size);
+ memory_region_init_ram(prom, "Leon3.bios", prom_size);
+ vmstate_register_ram_global(prom);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
reset_info->flash_base = flash_base;
- memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
+ memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
reset_info->flash_base = flash_base;
- memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
+ memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Setup CPU & memory */
cpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
- memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
+ memory_region_init_ram(rom, "mainstone.rom", MAINSTONE_ROM);
+ vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
/* TODO: Configure BARs. */
/* DRAM at 0x40000000 */
- memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
+ memory_region_init_ram(ram, "mcf5208.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */
- memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
+ memory_region_init_ram(sram, "mcf5208.sram", 16384);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
sysbus_init_mmio(dev, &s->regs_region);
/* register buffers memory */
- memory_region_init_ram(&s->buffers, NULL, "milkymist-minimac2.buffers",
+ memory_region_init_ram(&s->buffers, "milkymist-minimac2.buffers",
buffers_size);
+ vmstate_register_ram_global(&s->buffers);
s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
sysbus_init_mmio(dev, &s->regs_region);
/* register pmem and dmem */
- memory_region_init_ram(&s->pmem, NULL, "milkymist-softusb.pmem",
+ memory_region_init_ram(&s->pmem, "milkymist-softusb.pmem",
s->pmem_size);
+ vmstate_register_ram_global(&s->pmem);
sysbus_add_memory(dev, s->pmem_base, &s->pmem);
- memory_region_init_ram(&s->dmem, NULL, "milkymist-softusb.dmem",
+ memory_region_init_ram(&s->dmem, "milkymist-softusb.dmem",
s->dmem_size);
+ vmstate_register_ram_global(&s->dmem);
sysbus_add_memory(dev, s->dmem_base, &s->dmem);
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
cpu_lm32_set_phys_msb_ignore(env, 1);
- memory_region_init_ram(phys_sdram, NULL, "milkymist.sdram", sdram_size);
+ memory_region_init_ram(phys_sdram, "milkymist.sdram", sdram_size);
+ vmstate_register_ram_global(phys_sdram);
memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram);
dinfo = drive_get(IF_PFLASH, 0, 0);
bios_size = 1024 * 1024;
/* allocate RAM */
- memory_region_init_ram(ram, NULL, "fulong2e.ram", ram_size);
- memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size);
+ memory_region_init_ram(ram, "fulong2e.ram", ram_size);
+ vmstate_register_ram_global(ram);
+ memory_region_init_ram(bios, "fulong2e.bios", bios_size);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(address_space_mem, 0, ram);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
- memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
+ memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space, 0, ram);
- memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
+ memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
- memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
+ memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
+ vmstate_register_ram_global(rom_mr);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- memory_region_init_ram(ram, NULL, "mips_malta.ram", ram_size);
+ memory_region_init_ram(ram, "mips_malta.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(system_memory, 0, ram);
#ifdef TARGET_WORDS_BIGENDIAN
if (kernel_filename) {
/* Write a small bootloader to the flash location. */
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "mips_malta.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE);
/* Map the bios at two physical locations, as on the real board. */
fl_idx++;
} else {
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "mips_malta.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios_alias, "bios.1fc",
bios, 0, BIOS_SIZE);
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate RAM. */
- memory_region_init_ram(ram, NULL, "mips_mipssim.ram", ram_size);
- memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE);
+ memory_region_init_ram(ram, "mips_mipssim.ram", ram_size);
+ vmstate_register_ram_global(ram);
+ memory_region_init_ram(bios, "mips_mipssim.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(address_space_mem, 0, ram);
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- memory_region_init_ram(ram, NULL, "mips_r4k.ram", ram_size);
+ memory_region_init_ram(ram, "mips_r4k.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
#endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "mips_r4k.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
cpu_pic = arm_pic_init_cpu(env);
/* For now we use a fixed - the original - RAM size */
- memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
+ memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
- memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
+ memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
omap_clk_init(s);
/* Memory-mapped stuff */
- memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
+ memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
+ vmstate_register_ram_global(&s->emiff_ram);
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
- memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
+ memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
+ vmstate_register_ram_global(&s->imif_ram);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
omap_clk_init(s);
/* Memory-mapped stuff */
- memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size);
+ memory_region_init_ram(&s->sdram, "omap2.dram", s->sdram_size);
+ vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
- memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size);
+ memory_region_init_ram(&s->sram, "omap2.sram", s->sram_size);
+ vmstate_register_ram_global(&s->sram);
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
- memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size);
+ memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size);
+ vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
- memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size);
+ memory_region_init_ram(flash_1, "omap_sx1.flash1-0", flash1_size);
+ vmstate_register_ram_global(flash_1);
memory_region_set_readonly(flash_1, true);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
}
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
+ memory_region_init_ram(&s->ram, "onenand.ram", 0xc000 << s->shift);
+ vmstate_register_ram_global(&s->ram);
ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);
s->boot[1] = ram + (0x8000 << s->shift);
cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
- memory_region_init_ram(flash, NULL, "palmte.flash", flash_size);
+ memory_region_init_ram(flash, "palmte.flash", flash_size);
+ vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash);
* with older qemus that used qemu_ram_alloc().
*/
ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "pc.ram",
+ memory_region_init_ram(ram, "pc.ram",
below_4g_mem_size + above_4g_mem_size);
+ vmstate_register_ram_global(ram);
*ram_memory = ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
goto bios_error;
}
bios = g_malloc(sizeof(*bios));
- memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
+ memory_region_init_ram(bios, "pc.bios", bios_size);
+ vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
if (ret != 0) {
memory_region_set_readonly(isa_bios, true);
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
- memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
+ memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
+ vmstate_register_ram_global(option_rom_mr);
memory_region_add_subregion_overlap(rom_memory,
PC_ROM_MIN_VGA,
option_rom_mr,
else
snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
pdev->has_rom = true;
- memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
+ memory_region_init_ram(&pdev->rom, name, size);
+ vmstate_register_ram(&pdev->rom, &pdev->qdev);
ptr = memory_region_get_ram_ptr(&pdev->rom);
load_image(path, ptr);
g_free(path);
if (!pdev->has_rom)
return;
+ vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
memory_region_destroy(&pdev->rom);
pdev->has_rom = false;
}
qemu_register_reset(main_cpu_reset, env);
/* Attach emulated BRAM through the LMB. */
- memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
+ memory_region_init_ram(phys_lmb_bram, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
+ vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
- memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size);
+ memory_region_init_ram(phys_ram, "petalogix_ml605.ram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
qemu_register_reset(main_cpu_reset, env);
/* Attach emulated BRAM through the LMB. */
- memory_region_init_ram(phys_lmb_bram, NULL,
+ memory_region_init_ram(phys_lmb_bram,
"petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE);
+ vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
- memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
- ram_size);
+ memory_region_init_ram(phys_ram, "petalogix_s3adsp1800.ram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
memory_region_init_rom_device(
&pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
- qdev, name, size);
+ name, size);
+ vmstate_register_ram(&pfl->mem, qdev);
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
memory_region_add_subregion(get_system_memory(), base, &pfl->mem);
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
if (ret < 0) {
memory_region_del_subregion(get_system_memory(), &pfl->mem);
+ vmstate_unregister_ram(&pfl->mem, qdev);
memory_region_destroy(&pfl->mem);
g_free(pfl);
return NULL;
pfl = g_malloc0(sizeof(pflash_t));
memory_region_init_rom_device(
&pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl,
- qdev, name, size);
+ name, size);
+ vmstate_register_ram(&pfl->orig_mem, qdev);
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
pfl->base = base;
pfl->chip_len = chip_len;
MemoryRegion *sysmem = get_system_memory();
/* XXX: fix this */
- memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ memory_region_init_ram(&ram_memories[0], "ef405ep.ram", 0x08000000);
+ vmstate_register_ram_global(&ram_memories[0]);
ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * 1024;
- memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size);
+ memory_region_init_ram(sram, "ef405ep.sram", sram_size);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, 0xFFF00000, sram);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "ef405ep.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- memory_region_init_ram(&ram_memories[0], NULL,
+ memory_region_init_ram(&ram_memories[0],
"taihu_405ep.ram-0", 0x04000000);
+ vmstate_register_ram_global(&ram_memories[0]);
ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
- memory_region_init_ram(&ram_memories[1], NULL,
+ memory_region_init_ram(&ram_memories[1],
"taihu_405ep.ram-1", 0x04000000);
+ vmstate_register_ram_global(&ram_memories[1]);
ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
ram_size = 0x08000000;
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "taihu_405ep.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
ocm = g_malloc0(sizeof(ppc405_ocm_t));
/* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
+ memory_region_init_ram(&ocm->isarc_ram, "ppc405.ocm", 4096);
+ vmstate_register_ram_global(&ocm->isarc_ram);
memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
0, 4096);
qemu_register_reset(&ocm_reset, ocm);
if (bank_size <= size_left) {
char name[32];
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_ram(&ram_memories[i], NULL, name, bank_size);
+ memory_region_init_ram(&ram_memories[i], name, bank_size);
+ vmstate_register_ram_global(&ram_memories[i]);
ram_bases[i] = base;
ram_sizes[i] = bank_size;
base += ram_size;
}
/* allocate RAM */
- memory_region_init_ram(ram, NULL, "ppc_core99.ram", ram_size);
+ memory_region_init_ram(ram, "ppc_core99.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(get_system_memory(), 0, ram);
/* allocate and load BIOS */
- memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
exit(1);
}
- memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size);
+ memory_region_init_ram(ram, "ppc_heathrow.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(sysmem, 0, ram);
/* allocate and load BIOS */
- memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "ppc_heathrow.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
}
/* allocate RAM */
- memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
+ memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(sysmem, 0, ram);
/* allocate and load BIOS */
- memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
+ vmstate_register_ram_global(bios);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
ram_size &= ~(RAM_SIZES_ALIGN - 1);
/* Register Memory */
- memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
+ memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
/* MPIC */
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
- memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
+ memory_region_init_ram(&s->sdram, "pxa270.sdram", sdram_size);
+ vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
- memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
+ memory_region_init_ram(&s->internal, "pxa270.internal", 0x40000);
+ vmstate_register_ram_global(&s->internal);
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
&s->internal);
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
- memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
+ memory_region_init_ram(&s->sdram, "pxa255.sdram", sdram_size);
+ vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
- memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
+ memory_region_init_ram(&s->internal, "pxa255.internal",
PXA2XX_INTERNAL_SIZE);
+ vmstate_register_ram_global(&s->internal);
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
&s->internal);
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
qxl->rom_size = qxl_rom_size();
- memory_region_init_ram(&qxl->rom_bar, &qxl->pci.qdev, "qxl.vrom",
- qxl->rom_size);
+ memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
+ vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
init_qxl_rom(qxl);
init_qxl_ram(qxl);
qxl->vram_size = 4096;
}
qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
- memory_region_init_ram(&qxl->vram_bar, &qxl->pci.qdev, "qxl.vram",
- qxl->vram_size);
+ memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
+ vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
if (qxl->revision == 1) {
ram_size = 16 * 1024 * 1024;
}
qxl->vga.vram_size = ram_size;
- memory_region_init_ram(&qxl->vga.vram, &qxl->pci.qdev, "qxl.vgavram",
- qxl->vga.vram_size);
+ memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
+ vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
return qxl_init_common(qxl);
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate memory space */
- memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE);
+ memory_region_init_ram(sdram, "r2d.sdram", SDRAM_SIZE);
+ vmstate_register_ram_global(sdram);
memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */
s = sh7750_init(env, address_space_mem);
/* Core tile RAM. */
low_ram_size = ram_size - 0x20000000;
ram_size = 0x20000000;
- memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
+ memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
+ vmstate_register_ram_global(ram_lo);
memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
}
- memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
+ memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
+ vmstate_register_ram_global(ram_hi);
low_ram_size = ram_size;
if (low_ram_size > 0x10000000)
low_ram_size = 0x10000000;
startup code. I guess this works on real hardware because the
BootROM happens to be in ROM/flash or in memory that isn't clobbered
until after Linux boots the secondary CPUs. */
- memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
+ memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
+ vmstate_register_ram_global(ram_hack);
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
realview_binfo.ram_size = ram_size;
s390_bus = s390_virtio_bus_init(&my_ram_size);
/* allocate RAM */
- memory_region_init_ram(ram, NULL, "s390.ram", my_ram_size);
+ memory_region_init_ram(ram, "s390.ram", my_ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(sysmem, 0, ram);
/* clear virtio region */
/* Allocate memory space */
printf("Allocating ROM\n");
- memory_region_init_ram(rom, NULL, "shix.rom", 0x4000);
+ memory_region_init_ram(rom, "shix.rom", 0x4000);
+ vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(sysmem, 0x00000000, rom);
printf("Allocating SDRAM 1\n");
- memory_region_init_ram(&sdram[0], NULL, "shix.sdram1", 0x01000000);
+ memory_region_init_ram(&sdram[0], "shix.sdram1", 0x01000000);
+ vmstate_register_ram_global(&sdram[0]);
memory_region_add_subregion(sysmem, 0x08000000, &sdram[0]);
printf("Allocating SDRAM 2\n");
- memory_region_init_ram(&sdram[1], NULL, "shix.sdram2", 0x01000000);
+ memory_region_init_ram(&sdram[1], "shix.sdram2", 0x01000000);
+ vmstate_register_ram_global(&sdram[1]);
memory_region_add_subregion(sysmem, 0x0c000000, &sdram[1]);
/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
s->dc_crt_control = 0x00010000;
/* allocate local memory */
- memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
+ memory_region_init_ram(&s->local_mem_region, "sm501.local",
local_mem_bytes);
+ vmstate_register_ram_global(&s->local_mem_region);
s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
ram_addr_t nonrma_base = rma_alloc_size;
ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
- memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size);
+ memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(sysmem, nonrma_base, ram);
}
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
- memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM);
+ memory_region_init_ram(rom, "spitz.rom", SPITZ_ROM);
+ vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
exit(1);
}
- memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size);
+ memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
+ vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
pic = arm_pic_init_cpu(s->env);
{
IDRegState *s = FROM_SYSBUS(IDRegState, dev);
- memory_region_init_ram(&s->mem, NULL, "sun4m.idreg", sizeof(idreg_data));
+ memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
+ vmstate_register_ram_global(&s->mem);
memory_region_set_readonly(&s->mem, true);
sysbus_init_mmio(dev, &s->mem);
return 0;
{
AFXState *s = FROM_SYSBUS(AFXState, dev);
- memory_region_init_ram(&s->mem, NULL, "sun4m.afx", 4);
+ memory_region_init_ram(&s->mem, "sun4m.afx", 4);
+ vmstate_register_ram_global(&s->mem);
sysbus_init_mmio(dev, &s->mem);
return 0;
}
{
PROMState *s = FROM_SYSBUS(PROMState, dev);
- memory_region_init_ram(&s->prom, NULL, "sun4m.prom", PROM_SIZE_MAX);
+ memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
+ vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
return 0;
{
RamDevice *d = FROM_SYSBUS(RamDevice, dev);
- memory_region_init_ram(&d->ram, NULL, "sun4m.ram", d->size);
+ memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
+ vmstate_register_ram_global(&d->ram);
sysbus_init_mmio(dev, &d->ram);
return 0;
}
{
PROMState *s = FROM_SYSBUS(PROMState, dev);
- memory_region_init_ram(&s->prom, NULL, "sun4u.prom", PROM_SIZE_MAX);
+ memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
+ vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
return 0;
{
RamDevice *d = FROM_SYSBUS(RamDevice, dev);
- memory_region_init_ram(&d->ram, NULL, "sun4u.ram", d->size);
+ memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
+ vmstate_register_ram_global(&d->ram);
sysbus_init_mmio(dev, &d->ram);
return 0;
}
memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
memory_region_add_subregion(sysmem, base, &s->iomem);
- memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000);
+ memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
+ vmstate_register_ram_global(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
s->scr_width = 480;
int size;
uint8_t *vram_base;
- memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram",
+ memory_region_init_ram(&s->vram_mem, "tcx.vram",
s->vram_size * (1 + 4 + 4));
+ vmstate_register_ram_global(&s->vram_mem);
vram_base = memory_region_get_ram_ptr(&s->vram_mem);
/* 8-bit plane */
cpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
- memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM);
+ memory_region_init_ram(rom, "tosa.rom", TOSA_ROM);
+ vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- memory_region_init_ram(ram, NULL, "versatile.ram", ram_size);
+ memory_region_init_ram(ram, "versatile.ram", ram_size);
+ vmstate_register_ram_global(ram);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, ram);
exit(1);
}
- memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
+ memory_region_init_ram(ram, "vexpress.highmem", ram_size);
+ vmstate_register_ram_global(ram);
low_ram_size = ram_size;
if (low_ram_size > 0x4000000) {
low_ram_size = 0x4000000;
/* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */
/* CS2: SRAM : 0x48000000 .. 0x4a000000 */
sram_size = 0x2000000;
- memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
+ memory_region_init_ram(sram, "vexpress.sram", sram_size);
+ vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, 0x48000000, sram);
/* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
/* 0x4c000000 Video RAM */
vram_size = 0x800000;
- memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
+ memory_region_init_ram(vram, "vexpress.vram", vram_size);
+ vmstate_register_ram_global(vram);
memory_region_add_subregion(sysmem, 0x4c000000, vram);
/* 0x4e000000 LAN9118 Ethernet */
startup code. I guess this works on real hardware because the
BootROM happens to be in ROM/flash or in memory that isn't clobbered
until after Linux boots the secondary CPUs. */
- memory_region_init_ram(hackram, NULL, "vexpress.hack", 0x1000);
+ memory_region_init_ram(hackram, "vexpress.hack", 0x1000);
+ vmstate_register_ram_global(hackram);
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, hackram);
vexpress_binfo.ram_size = ram_size;
#else
s->is_vbe_vmstate = 0;
#endif
- memory_region_init_ram(&s->vram, NULL, "vga.vram", vga_ram_size);
+ memory_region_init_ram(&s->vram, "vga.vram", vga_ram_size);
+ vmstate_register_ram_global(&s->vram);
xen_register_framebuffer(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
s->vram_size = vga_ram_size;
env = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000);
qemu_register_reset(main_cpu_reset, env);
- memory_region_init_ram(phys_ram, NULL, "ram", ram_size);
+ memory_region_init_ram(phys_ram, "ram", ram_size);
+ vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
s->fifo_size = SVGA_FIFO_SIZE;
- memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size);
+ memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
+ vmstate_register_ram_global(&s->fifo_ram);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
vga_common_init(&s->vga, vga_ram_size);
sysbus_mmio_get_region(s, 1));
ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "open_eth.ram", 16384);
+ memory_region_init_ram(ram, "open_eth.ram", 16384);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space, buffers, ram);
}
}
ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "lx60.dram", ram_size);
+ memory_region_init_ram(ram, "lx60.dram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(system_memory, 0, ram);
system_io = g_malloc(sizeof(*system_io));
/* Use presence of kernel file name as 'boot from SRAM' switch. */
if (kernel_filename) {
rom = g_malloc(sizeof(*rom));
- memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size);
+ memory_region_init_ram(rom, "lx60.sram", board->sram_size);
+ vmstate_register_ram_global(rom);
memory_region_add_subregion(system_memory, 0xfe000000, rom);
/* Put kernel bootparameters to the end of that SRAM */
}
ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size);
+ memory_region_init_ram(ram, "xtensa.sram", ram_size);
+ vmstate_register_ram_global(ram);
memory_region_add_subregion(get_system_memory(), 0, ram);
rom = g_malloc(sizeof(*rom));
- memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000);
+ memory_region_init_ram(rom, "xtensa.rom", 0x1000);
+ vmstate_register_ram_global(rom);
memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
if (kernel_filename) {
}
}
-static void memory_region_prepare_ram_addr(MemoryRegion *mr);
-
static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
{
- ram_addr_t phys_offset, region_offset;
-
- memory_region_prepare_ram_addr(fr->mr);
-
- phys_offset = fr->mr->ram_addr;
- region_offset = fr->offset_in_region;
- /* cpu_register_physical_memory_log() wants region_offset for
- * mmio, but prefers offseting phys_offset for RAM. Humour it.
- */
- if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
- phys_offset += region_offset;
- region_offset = 0;
- }
-
- if (!fr->readable) {
- phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD;
- }
-
- if (fr->readonly) {
- phys_offset |= IO_MEM_ROM;
- }
+ MemoryRegionSection section = {
+ .mr = fr->mr,
+ .offset_within_address_space = int128_get64(fr->addr.start),
+ .offset_within_region = fr->offset_in_region,
+ .size = int128_get64(fr->addr.size),
+ };
- cpu_register_physical_memory_log(int128_get64(fr->addr.start),
- int128_get64(fr->addr.size),
- phys_offset,
- region_offset,
- fr->dirty_log_mask);
+ cpu_register_physical_memory_log(§ion, fr->readable, fr->readonly);
}
static void as_memory_range_del(AddressSpace *as, FlatRange *fr)
{
- cpu_register_physical_memory(int128_get64(fr->addr.start),
- int128_get64(fr->addr.size),
- IO_MEM_UNASSIGNED);
+ MemoryRegionSection section = {
+ .mr = &io_mem_unassigned,
+ .offset_within_address_space = int128_get64(fr->addr.start),
+ .offset_within_region = int128_get64(fr->addr.start),
+ .size = int128_get64(fr->addr.size),
+ };
+
+ cpu_register_physical_memory_log(§ion, true, false);
}
static void as_memory_log_start(AddressSpace *as, FlatRange *fr)
static void memory_region_destructor_rom_device(MemoryRegion *mr)
{
qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
- cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
+ cpu_unregister_io_memory(mr->ram_addr & ~TARGET_PAGE_MASK);
+}
+
+static bool memory_region_wrong_endianness(MemoryRegion *mr)
+{
+#ifdef TARGET_BIG_ENDIAN
+ return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
+#else
+ return mr->ops->endianness == DEVICE_BIG_ENDIAN;
+#endif
}
void memory_region_init(MemoryRegion *mr,
}
mr->addr = 0;
mr->offset = 0;
+ mr->subpage = false;
mr->enabled = true;
mr->terminates = false;
mr->ram = false;
mr->readable = true;
mr->readonly = false;
+ mr->rom_device = false;
mr->destructor = memory_region_destructor_none;
mr->priority = 0;
mr->may_overlap = false;
return true;
}
-static uint32_t memory_region_read_thunk_n(void *_mr,
- target_phys_addr_t addr,
- unsigned size)
+static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ unsigned size)
{
- MemoryRegion *mr = _mr;
uint64_t data = 0;
if (!memory_region_access_valid(mr, addr, size, false)) {
return data;
}
-static void memory_region_write_thunk_n(void *_mr,
- target_phys_addr_t addr,
- unsigned size,
- uint64_t data)
+static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
+{
+ if (memory_region_wrong_endianness(mr)) {
+ switch (size) {
+ case 1:
+ break;
+ case 2:
+ *data = bswap16(*data);
+ break;
+ case 4:
+ *data = bswap32(*data);
+ default:
+ abort();
+ }
+ }
+}
+
+static uint64_t memory_region_dispatch_read(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ unsigned size)
{
- MemoryRegion *mr = _mr;
+ uint64_t ret;
+
+ ret = memory_region_dispatch_read1(mr, addr, size);
+ adjust_endianness(mr, &ret, size);
+ return ret;
+}
+static void memory_region_dispatch_write(MemoryRegion *mr,
+ target_phys_addr_t addr,
+ uint64_t data,
+ unsigned size)
+{
if (!memory_region_access_valid(mr, addr, size, true)) {
return; /* FIXME: better signalling */
}
+ adjust_endianness(mr, &data, size);
+
if (!mr->ops->write) {
mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data);
return;
memory_region_write_accessor, mr);
}
-static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
-{
- return memory_region_read_thunk_n(mr, addr, 1);
-}
-
-static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr)
-{
- return memory_region_read_thunk_n(mr, addr, 2);
-}
-
-static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr)
-{
- return memory_region_read_thunk_n(mr, addr, 4);
-}
-
-static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
- uint32_t data)
-{
- memory_region_write_thunk_n(mr, addr, 1, data);
-}
-
-static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr,
- uint32_t data)
-{
- memory_region_write_thunk_n(mr, addr, 2, data);
-}
-
-static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr,
- uint32_t data)
-{
- memory_region_write_thunk_n(mr, addr, 4, data);
-}
-
-static CPUReadMemoryFunc * const memory_region_read_thunk[] = {
- memory_region_read_thunk_b,
- memory_region_read_thunk_w,
- memory_region_read_thunk_l,
-};
-
-static CPUWriteMemoryFunc * const memory_region_write_thunk[] = {
- memory_region_write_thunk_b,
- memory_region_write_thunk_w,
- memory_region_write_thunk_l,
-};
-
-static void memory_region_prepare_ram_addr(MemoryRegion *mr)
-{
- if (mr->backend_registered) {
- return;
- }
-
- mr->destructor = memory_region_destructor_iomem;
- mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk,
- memory_region_write_thunk,
- mr,
- mr->ops->endianness);
- mr->backend_registered = true;
-}
-
void memory_region_init_io(MemoryRegion *mr,
const MemoryRegionOps *ops,
void *opaque,
mr->ops = ops;
mr->opaque = opaque;
mr->terminates = true;
- mr->backend_registered = false;
+ mr->destructor = memory_region_destructor_iomem;
+ mr->ram_addr = cpu_register_io_memory(mr);
}
void memory_region_init_ram(MemoryRegion *mr,
- DeviceState *dev,
const char *name,
uint64_t size)
{
mr->ram = true;
mr->terminates = true;
mr->destructor = memory_region_destructor_ram;
- mr->ram_addr = qemu_ram_alloc(dev, name, size, mr);
- mr->backend_registered = true;
+ mr->ram_addr = qemu_ram_alloc(size, mr);
}
void memory_region_init_ram_ptr(MemoryRegion *mr,
- DeviceState *dev,
const char *name,
uint64_t size,
void *ptr)
mr->ram = true;
mr->terminates = true;
mr->destructor = memory_region_destructor_ram_from_ptr;
- mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr, mr);
- mr->backend_registered = true;
+ mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
}
void memory_region_init_alias(MemoryRegion *mr,
void memory_region_init_rom_device(MemoryRegion *mr,
const MemoryRegionOps *ops,
void *opaque,
- DeviceState *dev,
const char *name,
uint64_t size)
{
mr->ops = ops;
mr->opaque = opaque;
mr->terminates = true;
+ mr->rom_device = true;
mr->destructor = memory_region_destructor_rom_device;
- mr->ram_addr = qemu_ram_alloc(dev, name, size, mr);
- mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk,
- memory_region_write_thunk,
- mr,
- mr->ops->endianness);
- mr->ram_addr |= IO_MEM_ROMD;
- mr->backend_registered = true;
+ mr->ram_addr = qemu_ram_alloc(size, mr);
+ mr->ram_addr |= cpu_register_io_memory(mr);
}
void memory_region_destroy(MemoryRegion *mr)
return int128_get64(mr->size);
}
+const char *memory_region_name(MemoryRegion *mr)
+{
+ return mr->name;
+}
+
bool memory_region_is_ram(MemoryRegion *mr)
{
return mr->ram;
ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
{
- assert(mr->backend_registered);
return mr->ram_addr;
}
{
MemoryListener *listener;
+ cpu_physical_memory_set_dirty_tracking(1);
global_dirty_log = true;
QLIST_FOREACH(listener, &memory_listeners, link) {
listener->log_global_start(listener);
QLIST_FOREACH(listener, &memory_listeners, link) {
listener->log_global_stop(listener);
}
+ cpu_physical_memory_set_dirty_tracking(0);
}
static void listener_add_address_space(MemoryListener *listener,
memory_region_update_topology(NULL);
}
+uint64_t io_mem_read(int io_index, target_phys_addr_t addr, unsigned size)
+{
+ return memory_region_dispatch_read(io_mem_region[io_index], addr, size);
+}
+
+void io_mem_write(int io_index, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ memory_region_dispatch_write(io_mem_region[io_index], addr, val, size);
+}
+
typedef struct MemoryRegionList MemoryRegionList;
struct MemoryRegionList {
Int128 size;
target_phys_addr_t addr;
target_phys_addr_t offset;
- bool backend_registered;
void (*destructor)(MemoryRegion *mr);
ram_addr_t ram_addr;
IORange iorange;
+ bool subpage;
bool terminates;
bool readable;
bool ram;
bool readonly; /* For RAM regions */
bool enabled;
+ bool rom_device;
MemoryRegion *alias;
target_phys_addr_t alias_offset;
unsigned priority;
* region will modify memory directly.
*
* @mr: the #MemoryRegion to be initialized.
- * @dev: a device associated with the region; may be %NULL.
- * @name: the name of the region; the pair (@dev, @name) must be globally
- * unique. The name is part of the save/restore ABI and so cannot be
- * changed.
+ * @name: the name of the region.
* @size: size of the region.
*/
void memory_region_init_ram(MemoryRegion *mr,
- DeviceState *dev, /* FIXME: layering violation */
const char *name,
uint64_t size);
* memory directly.
*
* @mr: the #MemoryRegion to be initialized.
- * @dev: a device associated with the region; may be %NULL.
- * @name: the name of the region; the pair (@dev, @name) must be globally
- * unique. The name is part of the save/restore ABI and so cannot be
- * changed.
+ * @name: the name of the region.
* @size: size of the region.
* @ptr: memory to be mapped; must contain at least @size bytes.
*/
void memory_region_init_ram_ptr(MemoryRegion *mr,
- DeviceState *dev, /* FIXME: layering violation */
const char *name,
uint64_t size,
void *ptr);
*
* @mr: the #MemoryRegion to be initialized.
* @ops: callbacks for write access handling.
- * @dev: a device associated with the region; may be %NULL.
- * @name: the name of the region; the pair (@dev, @name) must be globally
- * unique. The name is part of the save/restore ABI and so cannot be
- * changed.
+ * @name: the name of the region.
* @size: size of the region.
*/
void memory_region_init_rom_device(MemoryRegion *mr,
const MemoryRegionOps *ops,
void *opaque,
- DeviceState *dev, /* FIXME: layering violation */
const char *name,
uint64_t size);
*/
bool memory_region_is_ram(MemoryRegion *mr);
+/**
+ * memory_region_name: get a memory region's name
+ *
+ * Returns the string that was used to initialize the memory region.
+ *
+ * @mr: the memory region being queried
+ */
+const char *memory_region_name(MemoryRegion *mr);
+
/**
* memory_region_is_logging: return whether a memory region is logging writes
*
#include "qemu-queue.h"
#include "qemu-timer.h"
#include "cpus.h"
+#include "memory.h"
#define SELF_ANNOUNCE_ROUNDS 5
g_free(available_snapshots);
}
+
+void vmstate_register_ram(MemoryRegion *mr, DeviceState *dev)
+{
+ qemu_ram_set_idstr(memory_region_get_ram_addr(mr),
+ memory_region_name(mr), dev);
+}
+
+void vmstate_unregister_ram(MemoryRegion *mr, DeviceState *dev)
+{
+ /* Nothing do to while the implementation is in RAMBlock */
+}
+
+void vmstate_register_ram_global(MemoryRegion *mr)
+{
+ vmstate_register_ram(mr, NULL);
+}
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu-timer.h"
+#include "memory.h"
#define DATA_SIZE (1 << SHIFT)
{
DATA_TYPE res;
int index;
- index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ index = physaddr & (IO_MEM_NB_ENTRIES - 1);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
env->mem_io_pc = (unsigned long)retaddr;
- if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
+ if (index != io_mem_ram.ram_addr && index != io_mem_rom.ram_addr
+ && index != io_mem_unassigned.ram_addr
+ && index != io_mem_notdirty.ram_addr
&& !can_do_io(env)) {
cpu_io_recompile(env, retaddr);
}
env->mem_io_vaddr = addr;
#if SHIFT <= 2
- res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
+ res = io_mem_read(index, physaddr, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
- res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
- res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
+ res = io_mem_read(index, physaddr, 4) << 32;
+ res |= io_mem_read(index, physaddr + 4, 4);
#else
- res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
- res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
+ res = io_mem_read(index, physaddr, 4);
+ res |= io_mem_read(index, physaddr + 4, 4) << 32;
#endif
#endif /* SHIFT > 2 */
return res;
void *retaddr)
{
int index;
- index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
+ index = physaddr & (IO_MEM_NB_ENTRIES - 1);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
- if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
+ if (index != io_mem_ram.ram_addr && index != io_mem_rom.ram_addr
+ && index != io_mem_unassigned.ram_addr
+ && index != io_mem_notdirty.ram_addr
&& !can_do_io(env)) {
cpu_io_recompile(env, retaddr);
}
env->mem_io_vaddr = addr;
env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
- io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
+ io_mem_write(index, physaddr, val, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
- io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
- io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
+ io_mem_write(index, physaddr, (val >> 32), 4);
+ io_mem_write(index, physaddr + 4, (uint32_t)val, 4);
#else
- io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
- io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
+ io_mem_write(index, physaddr, (uint32_t)val, 4);
+ io_mem_write(index, physaddr + 4, val >> 32, 4);
#endif
#endif /* SHIFT > 2 */
}
*/
block_len += HVM_BELOW_4G_MMIO_LENGTH;
}
- memory_region_init_ram(&ram_memory, NULL, "xen.ram", block_len);
+ memory_region_init_ram(&ram_memory, "xen.ram", block_len);
+ vmstate_register_ram_global(&ram_memory);
if (ram_size >= HVM_BELOW_4G_RAM_END) {
above_4g_mem_size = ram_size - HVM_BELOW_4G_RAM_END;
ram_addr_t size)
{
target_phys_addr_t npages = size >> TARGET_PAGE_BITS;
- target_phys_addr_t vram_offset = 0;
const int width = sizeof(unsigned long) * 8;
unsigned long bitmap[(npages + width - 1) / width];
int rc, i, j;
} else if (state->log_for_dirtybit != physmap) {
return -1;
}
- vram_offset = physmap->phys_offset;
rc = xc_hvm_track_dirty_vram(xen_xc, xen_domid,
start_addr >> TARGET_PAGE_BITS, npages,
while (map != 0) {
j = ffsl(map) - 1;
map &= ~(1ul << j);
- cpu_physical_memory_set_dirty(vram_offset + (i * width + j) * TARGET_PAGE_SIZE);
+ memory_region_set_dirty(framebuffer,
+ (i * width + j) * TARGET_PAGE_SIZE);
};
}
projects / mirror_qemu.git / commitdiff