/* request the emulator to transfer a new DMA memory block ASAP */
void DMA_schedule(int nchan)
{
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
+ CPUState *env = cpu_single_env;
+ if (env)
+ cpu_interrupt(env, CPU_INTERRUPT_EXIT);
}
static void dma_reset(void *opaque)
static void heathrow_pic_update(HeathrowPICS *s)
{
if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
}
static void pic_irq_request(void *opaque, int level)
{
+ CPUState *env = first_cpu;
if (level) {
- cpu_single_env->CP0_Cause |= 0x00000400;
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ env->CP0_Cause |= 0x00000400;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
- cpu_single_env->CP0_Cause &= ~0x00000400;
- cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ env->CP0_Cause &= ~0x00000400;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
void cpu_mips_store_compare (CPUState *env, uint32_t value)
{
cpu_mips_update_count(env, cpu_mips_get_count(env), value);
- cpu_single_env->CP0_Cause &= ~0x00008000;
- cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ env->CP0_Cause &= ~0x00008000;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
static void mips_timer_cb (void *opaque)
}
#endif
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
- cpu_single_env->CP0_Cause |= 0x00008000;
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ env->CP0_Cause |= 0x00008000;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
void cpu_mips_clock_init (CPUState *env)
int io_memory;
int linux_boot;
int ret;
+ CPUState *env;
printf("%s: start\n", __func__);
linux_boot = (kernel_filename != NULL);
+
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
bios_offset = ram_size + vga_ram_size;
BIOS_SIZE, bios_offset | IO_MEM_ROM);
#if 0
memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
- cpu_single_env->PC = 0x80010004;
+ env->PC = 0x80010004;
#else
- cpu_single_env->PC = 0xBFC00004;
+ env->PC = 0xBFC00004;
#endif
if (linux_boot) {
kernel_base = KERNEL_LOAD_ADDR;
initrd_base = 0;
initrd_size = 0;
}
- cpu_single_env->PC = KERNEL_LOAD_ADDR;
+ env->PC = KERNEL_LOAD_ADDR;
} else {
kernel_base = 0;
kernel_size = 0;
}
/* Init internal devices */
- cpu_mips_clock_init(cpu_single_env);
+ cpu_mips_clock_init(env);
cpu_mips_irqctrl_init();
/* Register 64 KB of ISA IO space at 0x14000000 */
cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
isa_mem_base = 0x10000000;
- isa_pic = pic_init(pic_irq_request, cpu_single_env);
+ isa_pic = pic_init(pic_irq_request, env);
pit = pit_init(0x40, 0);
serial_init(0x3f8, 4, serial_hds[0]);
vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
if (priority > dst->raised.priority) {
IRQ_get_next(opp, &dst->raised);
DPRINTF("Raise CPU IRQ\n");
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ /* XXX: choose the correct cpu */
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
}
/* XXX: Should be able to reset any CPU */
if (val & 1) {
DPRINTF("Reset CPU IRQ\n");
- // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
+ // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
}
break;
#if MAX_IPI > 0
src = &opp->src[n_IRQ];
if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
DPRINTF("Raise CPU IRQ\n");
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ /* XXX: choose cpu */
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
}
break;
static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
{
- return cpu_inb(cpu_single_env, addr);
+ return cpu_inb(NULL, addr);
}
static void isa_outb(uint32_t val, uint32_t addr)
{
- cpu_outb(cpu_single_env, addr, val);
+ cpu_outb(NULL, addr, val);
}
static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
{
- return cpu_inw(cpu_single_env, addr);
+ return cpu_inw(NULL, addr);
}
static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
{
- cpu_outw(cpu_single_env, addr, val);
+ cpu_outw(NULL, addr, val);
}
static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
{
- return cpu_inl(cpu_single_env, addr);
+ return cpu_inl(NULL, addr);
}
static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
{
- cpu_outl(cpu_single_env, addr, val);
+ cpu_outl(NULL, addr, val);
}
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
case KBD_CCMD_READ_OUTPORT:
/* XXX: check that */
#ifdef TARGET_I386
- val = 0x01 | (((cpu_single_env->a20_mask >> 20) & 1) << 1);
+ val = 0x01 | (ioport_get_a20() << 1);
#else
val = 0x01;
#endif
break;
#ifdef TARGET_I386
case KBD_CCMD_ENABLE_A20:
- cpu_x86_set_a20(cpu_single_env, 1);
+ ioport_set_a20(1);
break;
case KBD_CCMD_DISABLE_A20:
- cpu_x86_set_a20(cpu_single_env, 0);
+ ioport_set_a20(0);
break;
#endif
case KBD_CCMD_RESET:
break;
case KBD_CCMD_WRITE_OUTPORT:
#ifdef TARGET_I386
- cpu_x86_set_a20(cpu_single_env, (val >> 1) & 1);
+ ioport_set_a20((val >> 1) & 1);
#endif
if (!(val & 1)) {
qemu_system_reset_request();
const char *initrd_filename,
int is_heathrow)
{
+ CPUState *env;
char buf[1024];
SetIRQFunc *set_irq;
void *pic;
linux_boot = (kernel_filename != NULL);
+ /* init CPUs */
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+
+ /* Register CPU as a 74x/75x */
+ /* XXX: CPU model (or PVR) should be provided on command line */
+ // ppc_find_by_name("750gx", &def); // Linux boot OK
+ // ppc_find_by_name("750fx", &def); // Linux boot OK
+ /* Linux does not boot on 750cxe (and probably other 750cx based)
+ * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
+ */
+ // ppc_find_by_name("750cxe", &def);
+ // ppc_find_by_name("750p", &def);
+ // ppc_find_by_name("740p", &def);
+ ppc_find_by_name("750", &def);
+ // ppc_find_by_name("740", &def);
+ // ppc_find_by_name("G3", &def);
+ // ppc_find_by_name("604r", &def);
+ // ppc_find_by_name("604e", &def);
+ // ppc_find_by_name("604", &def);
+ if (def == NULL) {
+ cpu_abort(env, "Unable to find PowerPC CPU definition\n");
+ }
+ cpu_ppc_register(env, def);
+
+ /* Set time-base frequency to 100 Mhz */
+ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+
+ env->osi_call = vga_osi_call;
+
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
initrd_base = 0;
initrd_size = 0;
}
- /* Register CPU as a 74x/75x */
- /* XXX: CPU model (or PVR) should be provided on command line */
- // ppc_find_by_name("750gx", &def); // Linux boot OK
- // ppc_find_by_name("750fx", &def); // Linux boot OK
- /* Linux does not boot on 750cxe (and probably other 750cx based)
- * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
- */
- // ppc_find_by_name("750cxe", &def);
- // ppc_find_by_name("750p", &def);
- // ppc_find_by_name("740p", &def);
- ppc_find_by_name("750", &def);
- // ppc_find_by_name("740", &def);
- // ppc_find_by_name("G3", &def);
- // ppc_find_by_name("604r", &def);
- // ppc_find_by_name("604e", &def);
- // ppc_find_by_name("604", &def);
- if (def == NULL) {
- cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
- }
- cpu_ppc_register(cpu_single_env, def);
-
- /* Set time-base frequency to 100 Mhz */
- cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
-
- cpu_single_env->osi_call = vga_osi_call;
if (is_heathrow) {
isa_mem_base = 0x80000000;
static void pic_irq_request(void *opaque, int level)
{
if (level)
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
else
- cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
}
/* PCI intack register */
/* Special port 92 */
/* Check soft reset asked */
if (val & 0x01) {
- // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
+ // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
}
/* Check LE mode */
if (val & 0x02) {
break;
case 0x0814:
/* L2 invalidate register */
- // tlb_flush(cpu_single_env, 1);
+ // tlb_flush(first_cpu, 1);
break;
case 0x081C:
/* system control register */
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
+ CPUState *env;
char buf[1024];
m48t59_t *nvram;
int PPC_io_memory;
return;
linux_boot = (kernel_filename != NULL);
+
+ /* init CPUs */
+
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+
+ /* Register CPU as a 604 */
+ /* XXX: CPU model (or PVR) should be provided on command line */
+ // ppc_find_by_name("604r", &def);
+ // ppc_find_by_name("604e", &def);
+ ppc_find_by_name("604", &def);
+ if (def == NULL) {
+ cpu_abort(env, "Unable to find PowerPC CPU definition\n");
+ }
+ cpu_ppc_register(env, def);
+ /* Set time-base frequency to 100 Mhz */
+ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
initrd_size = 0;
}
- /* Register CPU as a 604 */
- /* XXX: CPU model (or PVR) should be provided on command line */
- // ppc_find_by_name("604r", &def);
- // ppc_find_by_name("604e", &def);
- ppc_find_by_name("604", &def);
- if (def == NULL) {
- cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n");
- }
- cpu_ppc_register(cpu_single_env, def);
- /* Set time-base frequency to 100 Mhz */
- cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
-
isa_mem_base = 0xc0000000;
pci_bus = pci_prep_init();
// pci_bus = i440fx_init();
vga_ram_size, 0, 0);
rtc_init(0x70, 8);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
- isa_pic = pic_init(pic_irq_request, cpu_single_env);
+ isa_pic = pic_init(pic_irq_request, first_cpu);
// pit = pit_init(0x40, 0);
serial_init(0x3f8, 4, serial_hds[0]);
static void slavio_check_interrupts(void *opaque)
{
+ CPUState *env;
SLAVIO_INTCTLState *s = opaque;
uint32_t pending = s->intregm_pending;
unsigned int i, max = 0;
max = intbit_to_level[i];
}
}
- if (cpu_single_env->interrupt_index == 0) {
+ env = first_cpu;
+ if (env->interrupt_index == 0) {
DPRINTF("Triggered pil %d\n", max);
#ifdef DEBUG_IRQ_COUNT
s->irq_count[max]++;
#endif
- cpu_single_env->interrupt_index = TT_EXTINT | max;
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+ env->interrupt_index = TT_EXTINT | max;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
else
- DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, cpu_single_env->interrupt_index);
+ DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
}
else
DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
slavio_set_power_fail(slavio_misc, 1);
}
+static void main_cpu_reset(void *opaque)
+{
+ CPUState *env = opaque;
+ cpu_reset(env);
+}
+
/* Sun4m hardware initialisation */
static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
+ CPUState *env;
char buf[1024];
int ret, linux_boot;
unsigned int i;
linux_boot = (kernel_filename != NULL);
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+ qemu_register_reset(main_cpu_reset, env);
+
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, 0);
{
}
+static void main_cpu_reset(void *opaque)
+{
+ CPUState *env = opaque;
+ cpu_reset(env);
+}
+
static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
+ CPUState *env;
char buf[1024];
m48t59_t *nvram;
int ret, linux_boot;
linux_boot = (kernel_filename != NULL);
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+ qemu_register_reset(main_cpu_reset, env);
+
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, 0);
/* XXX: currently only used for async signals (see signal.c) */
CPUState *global_env;
-/* used only if single thread */
-CPUState *cpu_single_env = NULL;
/* used to free thread contexts */
TaskState *first_task_state;
// ppc_find_by_name("604e", &def);
// ppc_find_by_name("604", &def);
if (def == NULL) {
- cpu_abort(cpu_single_env,
+ cpu_abort(env,
"Unable to find PowerPC CPU definition\n");
}
- cpu_ppc_register(cpu_single_env, def);
+ cpu_ppc_register(env, def);
for (i = 0; i < 32; i++) {
if (i != 12 && i != 6 && i != 13)
#endif
#if !defined(CONFIG_USER_ONLY)
if (env->tl == MAXTL) {
- cpu_abort(cpu_single_env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
+ cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
return;
}
#endif
#endif
#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
- cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
+ cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
return;
}
#endif
{
CPUSPARCState *env;
- cpu_exec_init();
-
- if (!(env = malloc(sizeof(CPUSPARCState))))
- return (NULL);
- cpu_single_env = env;
+ env = qemu_mallocz(sizeof(CPUSPARCState));
+ if (!env)
+ return NULL;
+ cpu_exec_init(env);
cpu_reset(env);
return (env);
}
//#define SIGTEST
-CPUState *cpu_single_env = NULL;
-
void cpu_outb(CPUState *env, int addr, int val)
{
fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);