x86, mce: make mce_disabled boolean

The mce_disabled on 32bit is a tristate variable [1,0,-1],
while 64bit version is boolean [0,1].
This patch makes mce_disabled always boolean, and use mce_p5_enabled
to indicate the third state instead.

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index aae6fe2112f98b5575dc207ef9edb6874772cd9f..6568cdedcd89620a1045e654e1cc61dd12f9ecdc 100644 (file)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -107,6 +107,7 @@ struct mce_log {
 #include <asm/atomic.h>
 
 extern int mce_disabled;
+extern int mce_p5_enabled;
 
 #ifdef CONFIG_X86_OLD_MCE
 void amd_mcheck_init(struct cpuinfo_x86 *c);
@@ -117,14 +118,11 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
 #ifdef CONFIG_X86_ANCIENT_MCE
 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 void winchip_mcheck_init(struct cpuinfo_x86 *c);
-extern int mce_p5_enable;
-static inline int mce_p5_enabled(void) { return mce_p5_enable; }
-static inline void enable_p5_mce(void) { mce_p5_enable = 1; }
+static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 #else
 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
-static inline int mce_p5_enabled(void) { return 0; }
-static inline void enable_p5_mce(void) { }
+static inline void enable_p5_mce(void) {}
 #endif
 
 /* Call the installed machine check handler for this CPU setup. */

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index faedd776847d0bc6d386111f889ad7a35719b080..6095e0296abdccdc60dc67f56cfe6f9b536a81ea 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1286,8 +1286,7 @@ static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
                return;
        switch (c->x86_vendor) {
        case X86_VENDOR_INTEL:
-               if (mce_p5_enabled())
-                       intel_p5_mcheck_init(c);
+               intel_p5_mcheck_init(c);
                break;
        case X86_VENDOR_CENTAUR:
                winchip_mcheck_init(c);
@@ -2002,7 +2001,7 @@ EXPORT_SYMBOL_GPL(nr_mce_banks);  /* non-fatal.o */
 /* This has to be run for each processor */
 void mcheck_init(struct cpuinfo_x86 *c)
 {
-       if (mce_disabled == 1)
+       if (mce_disabled)
                return;
 
        switch (c->x86_vendor) {
@@ -2032,10 +2031,9 @@ void mcheck_init(struct cpuinfo_x86 *c)
 
 static int __init mcheck_enable(char *str)
 {
-       mce_disabled = -1;
+       mce_p5_enabled = 1;
        return 1;
 }
-
 __setup("mce", mcheck_enable);
 
 #endif /* CONFIG_X86_OLD_MCE */

diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c
index 747853f9188d79e69017ffc5c7b726ebafa5f548..5c0e6533d9bcdcc18bf43ddeab16ba43cefed1d9 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/p5.c
+++ b/arch/x86/kernel/cpu/mcheck/p5.c
@@ -14,7 +14,7 @@
 #include <asm/msr.h>
 
 /* By default disabled */
-int            mce_p5_enable;
+int mce_p5_enabled __read_mostly;
 
 /* Machine check handler for Pentium class Intel CPUs: */
 static void pentium_machine_check(struct pt_regs *regs, long error_code)
@@ -42,15 +42,13 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
 {
        u32 l, h;
 
-       /* Check for MCE support: */
-       if (!cpu_has(c, X86_FEATURE_MCE))
+       /* Default P5 to off as its often misconnected: */
+       if (!mce_p5_enabled)
                return;
 
-#ifdef CONFIG_X86_OLD_MCE
-       /* Default P5 to off as its often misconnected: */
-       if (mce_disabled != -1)
+       /* Check for MCE support: */
+       if (!cpu_has(c, X86_FEATURE_MCE))
                return;
-#endif
 
        machine_check_vector = pentium_machine_check;
        /* Make sure the vector pointer is visible before we enable MCEs: */