Implement Process Priority Register as defined in the PowerPC 2.04 spec.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3282 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-ppc/op.c b/target-ppc/op.c
index 46843d790f9b70fd01dbc005538a12bbf8c3303d..fa8477ab9f9c2c3cdb5ee4cc4f834b4c375bf30e 100644 (file)
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -295,6 +295,14 @@ void OPPROTO op_store_xer (void)
     RETURN();
 }
 
+#if defined(TARGET_PPC64)
+void OPPROTO op_store_pri (void)
+{
+    do_store_pri(PARAM1);
+    RETURN();
+}
+#endif
+
 #if !defined(CONFIG_USER_ONLY)
 /* Segment registers load and store */
 void OPPROTO op_load_sr (void)

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 08441caaec25f1771290c62b7ab045ef33e7c6dc..d75331722d5d0a99cf5a721868c871d1b41035d4 100644 (file)
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -112,6 +112,14 @@ void do_store_xer (void)
     xer_bc = (T0 >> XER_BC) & 0x7F;
 }
 
+#if defined(TARGET_PPC64)
+void do_store_pri (int prio)
+{
+    env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
+    env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
+}
+#endif
+
 void do_load_fpscr (void)
 {
     /* The 32 MSB of the target fpr are undefined.

diff --git a/target-ppc/op_helper.h b/target-ppc/op_helper.h
index 6c0d2fbf92acb925f779e5466ffd6cc5d008507b..c5b4f2d19bde30a1287005cfa6784ebfe95947a2 100644 (file)
--- a/target-ppc/op_helper.h
+++ b/target-ppc/op_helper.h
@@ -57,6 +57,9 @@ void do_load_cr (void);
 void do_store_cr (uint32_t mask);
 void do_load_xer (void);
 void do_store_xer (void);
+#if defined(TARGET_PPC64)
+void do_store_pri (int prio);
+#endif
 void do_load_fpscr (void);
 void do_store_fpscr (uint32_t mask);
 target_ulong ppc_load_dump_spr (int sprn);

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f4ff22e385085b0ea6c5cad3559f05a88b15581b..08cd92cde71826ccc03b395fff849dae991ed65b 100644 (file)
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1124,6 +1124,26 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
     } else if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_op_load_gpr_T0(rs);
         gen_set_Rc0(ctx);
+#if defined(TARGET_PPC64)
+    } else {
+        switch (rs) {
+        case 1:
+            /* Set process priority to low */
+            gen_op_store_pri(2);
+            break;
+        case 6:
+            /* Set process priority to medium-low */
+            gen_op_store_pri(3);
+            break;
+        case 2:
+            /* Set process priority to normal */
+            gen_op_store_pri(4);
+            break;
+        default:
+            /* nop */
+            break;
+        }
+#endif
     }
 }