drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw

v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)

v3: Avoid unnecessary read when it can be done by reading register once (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64caa470f2c6c5a0bda60c38cca753fc76704551..b8e2259fe9ee5d62b9cfda8cfd1a8d8c4fd61152 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -431,6 +431,7 @@
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE          (1<<9)
 #define   PIPE_CONTROL_NOTIFY                          (1<<8)
 #define   PIPE_CONTROL_FLUSH_ENABLE                    (1<<7) /* gen7+ */
+#define   PIPE_CONTROL_DC_FLUSH_ENABLE                 (1<<5)
 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE             (1<<4)
 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE          (1<<3)
 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE          (1<<2)
@@ -5811,6 +5812,7 @@ enum skl_disp_power_wells {
 
 #define GEN8_L3SQCREG4                         0xb118
 #define  GEN8_LQSC_RO_PERF_DIS                 (1<<27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES                (1<<21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0                           0x7300

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a1198baf34aaddbd98990e2e2d6ae49ff9bace58..2b65d29c48018e12256719f3750eae4c4cc26da8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1143,6 +1143,29 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
        /* WaDisableCtxRestoreArbitration:bdw,chv */
        wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
+       /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
+       if (IS_BROADWELL(ring->dev)) {
+               struct drm_i915_private *dev_priv = to_i915(ring->dev);
+               uint32_t l3sqc4_flush = (I915_READ(GEN8_L3SQCREG4) |
+                                        GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+               wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
+               wa_ctx_emit(batch, GEN8_L3SQCREG4);
+               wa_ctx_emit(batch, l3sqc4_flush);
+
+               wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6));
+               wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL |
+                                   PIPE_CONTROL_DC_FLUSH_ENABLE));
+               wa_ctx_emit(batch, 0);
+               wa_ctx_emit(batch, 0);
+               wa_ctx_emit(batch, 0);
+               wa_ctx_emit(batch, 0);
+
+               wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
+               wa_ctx_emit(batch, GEN8_L3SQCREG4);
+               wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES);
+       }
+
        /* Pad to end of cacheline */
        while (index % CACHELINE_DWORDS)
                wa_ctx_emit(batch, MI_NOOP);