clk: mediatek: add the option for determining PLL source clock

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f48df75cc901de3cde2c9c3cbdc5506aac5fa4c7..f10250dcece4ebd44e4216864da1a90f0a802dbd 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -218,6 +218,7 @@ struct mtk_pll_data {
        uint32_t pcw_reg;
        int pcw_shift;
        const struct mtk_pll_div_table *div_table;
+       const char *parent_name;
 };
 
 void mtk_clk_register_plls(struct device_node *node,

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 3c546bae69550055efebe7a02c0f278fc18f7b97..f54e4015b0b1f3c005e7d82b5fdffa6dc826a8ad 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
        init.name = data->name;
        init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
        init.ops = &mtk_pll_ops;
-       init.parent_names = &parent_name;
+       if (data->parent_name)
+               init.parent_names = &data->parent_name;
+       else
+               init.parent_names = &parent_name;
        init.num_parents = 1;
 
        clk = clk_register(NULL, &pll->hw);