clk: tegra20/30: Don't pre-initialize displays parent clock

Both Tegra20 and Tegra30 are initializing display's parent clock
incorrectly because PLLP is running at 216/408MHz while display rate is
set to 600MHz, but pre-setting the parent isn't needed at all because
display driver selects proper parent anyways.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 4d8222f5c63893ea348ca0003a7ace0b5b487ab4..0c14fb5703431cd0bc93bc16336f3e38690befa7 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1046,8 +1046,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
        { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
        { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
-       { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
-       { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
        { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
        { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
        { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c8bc18e4d7e5ac90f03d86ccdafec65fbad9f830..bd4d42005897e2903f21c487bc6f04cd2cf49f9f 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1251,8 +1251,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
        { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
        { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
-       { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
-       { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
        { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
        { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
        { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },