drm/i915: Record platform specific ppGTT size in intel_device_info

As the maximum addressable bits is determined by platform, record that
information in our static chipset tables. This has the advantage of
being clearly recorded in our capability dumps for dmesg, debugfs and
error states.

Based on a patch by Bob Paauwe.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190314223839.28258-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dccb6006aabfeb89d025a40396e64c8c9d0ad343..4864a35ddacacdf584d318699740268d2538cfae 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2452,7 +2452,7 @@ static inline unsigned int i915_sg_segment_size(void)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
 #define HAS_PPGTT(dev_priv) \
        (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dac08d9c3fab8a76eff0bbc77ce649f00714cb64..845d0ed5755bfeb17230a08bc8334f05b133c8e4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1538,10 +1538,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 
        ppgtt->vm.i915 = i915;
        ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-               1ULL << 48 :
-               1ULL << 32;
+       ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
 
        /* From bdw, there is support for read-only pages in the PPGTT. */
        ppgtt->vm.has_read_only = true;
@@ -1991,8 +1988,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 
        ppgtt->base.vm.i915 = i915;
        ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-       ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
+       ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
 
        i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
 

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3cf697e8f1fa767eac4a7b8f80000ec3d66e9c3f..a13ac0f3e528a2c830ec42bf064affd1dc6af97f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -349,7 +349,8 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
-       .ppgtt = INTEL_PPGTT_ALIASING, \
+       .ppgtt_type = INTEL_PPGTT_ALIASING, \
+       .ppgtt_size = 31, \
        I9XX_PIPE_OFFSETS, \
        I9XX_CURSOR_OFFSETS, \
        GEN_DEFAULT_PAGE_SIZES
@@ -394,7 +395,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
        .has_llc = 1, \
        .has_rc6 = 1, \
        .has_rc6p = 1, \
-       .ppgtt = INTEL_PPGTT_FULL, \
+       .ppgtt_type = INTEL_PPGTT_FULL, \
+       .ppgtt_size = 31, \
        IVB_PIPE_OFFSETS, \
        IVB_CURSOR_OFFSETS, \
        GEN_DEFAULT_PAGE_SIZES
@@ -447,7 +449,8 @@ static const struct intel_device_info intel_valleyview_info = {
        .has_rc6 = 1,
        .display.has_gmch = 1,
        .display.has_hotplug = 1,
-       .ppgtt = INTEL_PPGTT_FULL,
+       .ppgtt_type = INTEL_PPGTT_FULL,
+       .ppgtt_size = 31,
        .has_snoop = true,
        .has_coherent_ggtt = false,
        .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
@@ -495,7 +498,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
        .page_sizes = I915_GTT_PAGE_SIZE_4K | \
                      I915_GTT_PAGE_SIZE_2M, \
        .has_logical_ring_contexts = 1, \
-       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_size = 48, \
        .has_64bit_reloc = 1, \
        .has_reset_engine = 1
 
@@ -540,7 +544,8 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_rc6 = 1,
        .has_logical_ring_contexts = 1,
        .display.has_gmch = 1,
-       .ppgtt = INTEL_PPGTT_FULL,
+       .ppgtt_type = INTEL_PPGTT_FULL,
+       .ppgtt_size = 32,
        .has_reset_engine = 1,
        .has_snoop = true,
        .has_coherent_ggtt = false,
@@ -616,7 +621,8 @@ static const struct intel_device_info intel_skylake_gt4_info = {
        .has_logical_ring_contexts = 1, \
        .has_logical_ring_preemption = 1, \
        .has_guc = 1, \
-       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+       .ppgtt_size = 48, \
        .has_reset_engine = 1, \
        .has_snoop = true, \
        .has_coherent_ggtt = false, \

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index aac19b1c419c6504db86bd8de885229d7c64f8dc..eddf83807957efc19f806bd7316bb1c60f2b0778 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -844,7 +844,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
        if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
                DRM_INFO("Disabling ppGTT for VT-d support\n");
-               info->ppgtt = INTEL_PPGTT_NONE;
+               info->ppgtt_type = INTEL_PPGTT_NONE;
        }
 
        /* Initialize command stream timestamp frequency */

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 047d10bdd45543344e0439f77129d3d31bfa347e..b57b34c96b3d4011e92216d6a294b4c4a95f3451 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,7 +76,7 @@ enum intel_platform {
        INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
+enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
        INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
@@ -162,7 +162,9 @@ struct intel_device_info {
        enum intel_platform platform;
        u32 platform_mask;
 
-       enum intel_ppgtt ppgtt;
+       enum intel_ppgtt_type ppgtt_type;
+       unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
+
        unsigned int page_sizes; /* page sizes supported by the HW */
 
        u32 display_mmio_offset;

diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 1e66cff985f8034d96023867188abb2a725e25d2..e8b3f417a122a4ebcac03a99442bdd9ab56cc51d 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1709,7 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
                return -ENOMEM;
 
        /* Pretend to be a device which supports the 48b PPGTT */
-       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+       mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;
+       mkwrite_device_info(dev_priv)->ppgtt_size = 48;
 
        mutex_lock(&dev_priv->drm.struct_mutex);
        ppgtt = i915_ppgtt_create(dev_priv, ERR_PTR(-ENODEV));