channel = acc->channel;
list_dma = acc->list_dma[acc->list_index];
list_cpu = acc->list_cpu[acc->list_index];
- dev_dbg(kdev->dev, "acc-irq: channel %d, list %d, virt %p, phys %x\n",
- channel, acc->list_index, list_cpu, list_dma);
+ dev_dbg(kdev->dev, "acc-irq: channel %d, list %d, virt %p, dma %pad\n",
+ channel, acc->list_index, list_cpu, &list_dma);
if (atomic_read(&acc->retrigger_count)) {
atomic_dec(&acc->retrigger_count);
__knav_acc_notify(range, acc);
u32 result;
dev_dbg(kdev->dev, "acc command %08x %08x %08x %08x %08x\n",
- cmd->command, cmd->queue_mask, cmd->list_phys,
+ cmd->command, cmd->queue_mask, cmd->list_dma,
cmd->queue_num, cmd->timer_config);
writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config);
writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num);
- writel_relaxed(cmd->list_phys, &pdsp->acc_command->list_phys);
+ writel_relaxed(cmd->list_dma, &pdsp->acc_command->list_dma);
writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask);
writel_relaxed(cmd->command, &pdsp->acc_command->command);
memset(cmd, 0, sizeof(*cmd));
cmd->command = acc->channel;
cmd->queue_mask = queue_mask;
- cmd->list_phys = acc->list_dma[0];
+ cmd->list_dma = (u32)acc->list_dma[0];
cmd->queue_num = info->list_entries << 16;
cmd->queue_num |= queue_base;
acc->list_cpu[1] = list_mem + list_size;
acc->list_dma[0] = list_dma;
acc->list_dma[1] = list_dma + list_size;
- dev_dbg(kdev->dev, "%s: channel %d, phys %08x, virt %8p\n",
- acc->name, acc->channel, list_dma, list_mem);
+ dev_dbg(kdev->dev, "%s: channel %d, dma %pad, virt %8p\n",
+ acc->name, acc->channel, &list_dma, list_mem);
}
range->ops = &knav_acc_range_ops;
list_add(&pool->region_inst, ®ion->pools);
dev_dbg(kdev->dev,
- "region %s (%d): size:%d, link:%d@%d, phys:%08x-%08x, virt:%p-%p\n",
+ "region %s (%d): size:%d, link:%d@%d, dma:%pad-%pad, virt:%p-%p\n",
region->name, id, region->desc_size, region->num_desc,
- region->link_index, region->dma_start, region->dma_end,
+ region->link_index, ®ion->dma_start, ®ion->dma_end,
region->virt_start, region->virt_end);
hw_desc_size = (region->desc_size / 16) - 1;
for_each_qmgr(kdev, qmgr) {
regs = qmgr->reg_region + id;
- writel_relaxed(region->dma_start, ®s->base);
+ writel_relaxed((u32)region->dma_start, ®s->base);
writel_relaxed(region->link_index, ®s->start_index);
writel_relaxed(hw_desc_size << 16 | hw_num_desc,
®s->size_count);
* queue_base specified => using internal or onchip
* link ram WARNING - we do not "reserve" this block
*/
- block->phys = (dma_addr_t)temp[0];
+ block->dma = (dma_addr_t)temp[0];
block->virt = NULL;
block->size = temp[1];
} else {
block->size = temp[1];
/* queue_base not specific => allocate requested size */
block->virt = dmam_alloc_coherent(kdev->dev,
- 8 * block->size, &block->phys,
+ 8 * block->size, &block->dma,
GFP_KERNEL);
if (!block->virt) {
dev_err(kdev->dev, "failed to alloc linkram\n");
for_each_qmgr(kdev, qmgr) {
block = &kdev->link_rams[0];
- dev_dbg(kdev->dev, "linkram0: phys:%x, virt:%p, size:%x\n",
- block->phys, block->virt, block->size);
- writel_relaxed(block->phys, &qmgr->reg_config->link_ram_base0);
+ dev_dbg(kdev->dev, "linkram0: dma:%pad, virt:%p, size:%x\n",
+ &block->dma, block->virt, block->size);
+ writel_relaxed((u32)block->dma, &qmgr->reg_config->link_ram_base0);
writel_relaxed(block->size, &qmgr->reg_config->link_ram_size0);
block++;
if (!block->size)
continue;
- dev_dbg(kdev->dev, "linkram1: phys:%x, virt:%p, size:%x\n",
- block->phys, block->virt, block->size);
- writel_relaxed(block->phys, &qmgr->reg_config->link_ram_base1);
+ dev_dbg(kdev->dev, "linkram1: dma:%pad, virt:%p, size:%x\n",
+ &block->dma, block->virt, block->size);
+ writel_relaxed(block->dma, &qmgr->reg_config->link_ram_base1);
}
return 0;