drm/i915: Use 0 for the unordered context

Since commit 078dec3326e2 ("dma-buf: add dma_fence_get_stub") the 0
fence context became an impossible match as it is used for an always
signaled fence. We can simplify our timeline tracking by knowing that 0
always means no match.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190819184404.24200-1-chris@chris-wilson.co.uk
Link: https://patchwork.freedesktop.org/patch/msgid/20190819175109.5241-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index 77944950d4c9d0add8edcc0cf614378a3865c7ed..835d6756ba4981a72fe281612992183f16af66fb 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -134,8 +134,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
                dma_fence_init(&clflush->dma,
                               &i915_clflush_ops,
                               &clflush_lock,
-                              to_i915(obj->base.dev)->mm.unordered_timeline,
-                              0);
+                              0, 0);
                i915_sw_fence_init(&clflush->wait, i915_clflush_notify);
 
                clflush->obj = i915_gem_object_get(obj);

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 2536d1f54629fe75d15b17d1bdb1cf99ba35e3ac..61d0ca5c57416a65991ab855b45721141d8b659d 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -267,7 +267,6 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
                                     struct i915_page_sizes *page_sizes,
                                     u32 value)
 {
-       struct drm_i915_private *i915 = to_i915(obj->base.dev);
        struct clear_pages_work *work;
        struct i915_sleeve *sleeve;
        int err;
@@ -290,11 +289,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
 
        init_irq_work(&work->irq_work, clear_pages_signal_irq_worker);
 
-       dma_fence_init(&work->dma,
-                      &clear_pages_work_ops,
-                      &fence_lock,
-                      i915->mm.unordered_timeline,
-                      0);
+       dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0);
        i915_sw_fence_init(&work->wait, clear_pages_work_notify);
 
        i915_gem_object_lock(obj);

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_fence.c b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
index cf0439e6be83a563a095e0d6378a5c43ee8dbe44..c788f86faba3b4150076cf04bb343d2e36063e45 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
@@ -69,8 +69,7 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object *obj)
 
        i915_sw_fence_init(&stub->chain, stub_notify);
        dma_fence_init(&stub->dma, &stub_fence_ops, &stub->chain.wait.lock,
-                      to_i915(obj->base.dev)->mm.unordered_timeline,
-                      0);
+                      0, 0);
 
        if (i915_sw_fence_await_reservation(&stub->chain,
                                            obj->base.resv, NULL,

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1031fc187652a8eec3e92b1b3f6f6f453b9e7d55..63682cb3658a2eba6237a46bb6d3b6c8d98734a1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -748,8 +748,6 @@ struct i915_gem_mm {
         */
        struct workqueue_struct *userptr_wq;
 
-       u64 unordered_timeline;
-
        /** Bit 6 swizzling required for X tiling */
        u32 bit_6_swizzle_x;
        /** Bit 6 swizzling required for Y tiling */

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 85a1de5d3eb3b912af235d3f77152e99d5b8182f..71af43db3befc9abab37bd749a12762d8670731e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1411,8 +1411,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
                mkwrite_device_info(dev_priv)->page_sizes =
                        I915_GTT_PAGE_SIZE_4K;
 
-       dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
-
        intel_timelines_init(dev_priv);
 
        ret = i915_gem_init_userptr(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index eabf85b9779f54b7358f5e989b2a82989444b151..ae3a60a0c392e96c5209b362e340916dc757a037 100644 (file)
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -915,7 +915,7 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
                        continue;
 
                /* Squash repeated waits to the same timelines */
-               if (fence->context != rq->i915->mm.unordered_timeline &&
+               if (fence->context &&
                    intel_timeline_sync_is_later(rq->timeline, fence))
                        continue;
 
@@ -929,7 +929,7 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
                        return ret;
 
                /* Record the latest fence used against each timeline */
-               if (fence->context != rq->i915->mm.unordered_timeline)
+               if (fence->context)
                        intel_timeline_sync_set(rq->timeline, fence);
        } while (--nchild);