PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS

The Broadcom Northstar2 SoC has a number of quirks for the PAXC
(internal/fake) PCI bus.  Specifically, the PCI config space is shared
between the root port and the first PF (ie., PF0), and a number of fields
are tied to zero (thus preventing them from being set).  These cannot be
"fixed" in device firmware, so we must fix them with a quirk.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 1800befa8b8baa1ca87052b7a4dc4e36cde9b2d8..c5ef20a6c937e3379a78402a878c8e6e225eced8 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2239,6 +2239,27 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
                         PCI_DEVICE_ID_TIGON3_5719,
                         quirk_brcm_5719_limit_mrrs);
 
+#ifdef CONFIG_PCIE_IPROC_PLATFORM
+static void quirk_paxc_bridge(struct pci_dev *pdev)
+{
+       /* The PCI config space is shared with the PAXC root port and the first
+        * Ethernet device.  So, we need to workaround this by telling the PCI
+        * code that the bridge is not an Ethernet device.
+        */
+       if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
+               pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
+
+       /* MPSS is not being set properly (as it is currently 0).  This is
+        * because that area of the PCI config space is hard coded to zero, and
+        * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
+        * so that the MPS can be set to the real max value.
+        */
+       pdev->pcie_mpss = 2;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
+#endif
+
 /* Originally in EDAC sources for i82875P:
  * Intel tells BIOS developers to hide device 6 which
  * configures the overflow device access containing