drm/amdkfd: fix cu mask for asics with wgps

GFX10 and up have work group processors (WGP) and WGP mode is the native
compile mode.

KFD and ROCr have no visibility into whether a dispatch is operating
in CU or WGP mode.

Enforce CU masking to be pairwise continguous in enablement and
round robin distribute CUs across the SEs in a pairwise manner to
assume WGP mode at all times.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index 49a283be6b574870e9192303123b1275abe36b63..623ccd227b7de058263941c7a300c6379c42458a 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -100,7 +100,9 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
 {
        struct kfd_cu_info cu_info;
        uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
-       int i, se, sh, cu, cu_bitmap_sh_mul;
+       bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
+       uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
+       int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;
 
        amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
 
@@ -167,13 +169,13 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
                se_mask[i] = 0;
 
        i = 0;
-       for (cu = 0; cu < 16; cu++) {
+       for (cu = 0; cu < 16; cu += inc) {
                for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
                        for (se = 0; se < cu_info.num_shader_engines; se++) {
                                if (cu_per_sh[se][sh] > cu) {
-                                       if (cu_mask[i / 32] & (1 << (i % 32)))
-                                               se_mask[se] |= 1 << (cu + sh * 16);
-                                       i++;
+                                       if (cu_mask[i / 32] & (en_mask << (i % 32)))
+                                               se_mask[se] |= en_mask << (cu + sh * 16);
+                                       i += inc;
                                        if (i == cu_mask_count)
                                                return;
                                }

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index c9c205df4a147b908e416f82b8c356b1b7b1c82d..6e3e7f54381b33dadd940c7a1f3dcff3ed32a04a 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -498,6 +498,21 @@ int pqm_update_mqd(struct process_queue_manager *pqm,
                return -EFAULT;
        }
 
+       /* ASICs that have WGPs must enforce pairwise enabled mask checks. */
+       if (minfo && minfo->update_flag == UPDATE_FLAG_CU_MASK && minfo->cu_mask.ptr &&
+                       KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
+               int i;
+
+               for (i = 0; i < minfo->cu_mask.count; i += 2) {
+                       uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
+
+                       if (cu_pair && cu_pair != 0x3) {
+                               pr_debug("CUs must be adjacent pairwise enabled.\n");
+                               return -EINVAL;
+                       }
+               }
+       }
+
        retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
                                                        pqn->q, minfo);
        if (retval != 0)