dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings

Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250)
Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
new file mode 100644 (file)
index 0000000..0cdf53f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+  - Jonathan Marek <jonathan@marek.ca>
+
+description: |
+  Qualcomm display clock control module which supports the clocks, resets and
+  power domains on SM8150 and SM8250.
+
+  See also:
+    dt-bindings/clock/qcom,dispcc-sm8150.h
+    dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm8150-dispcc
+      - qcom,sm8250-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY0
+      - description: Byte clock from DSI PHY1
+      - description: Pixel clock from DSI PHY1
+      - description: Link clock from DP PHY
+      - description: VCO DIV clock from DP PHY
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: dsi0_phy_pll_out_byteclk
+      - const: dsi0_phy_pll_out_dsiclk
+      - const: dsi1_phy_pll_out_byteclk
+      - const: dsi1_phy_pll_out_dsiclk
+      - const: dp_phy_pll_link_clk
+      - const: dp_phy_pll_vco_div_clk
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@af00000 {
+      compatible = "qcom,sm8250-dispcc";
+      reg = <0x0af00000 0x10000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&dsi0_phy 0>,
+               <&dsi0_phy 1>,
+               <&dsi1_phy 0>,
+               <&dsi1_phy 1>,
+               <&dp_phy 0>,
+               <&dp_phy 1>;
+      clock-names = "bi_tcxo",
+                    "dsi0_phy_pll_out_byteclk",
+                    "dsi0_phy_pll_out_dsiclk",
+                    "dsi1_phy_pll_out_byteclk",
+                    "dsi1_phy_pll_out_dsiclk",
+                    "dp_phy_pll_link_clk",
+                    "dp_phy_pll_vco_div_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
new file mode 120000 (symlink)
index 0000000..0312b45
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file

diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
new file mode 100644 (file)
index 0000000..fdaca6a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK                   0
+#define DISP_CC_MDSS_AHB_CLK_SRC               1
+#define DISP_CC_MDSS_BYTE0_CLK                 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC             3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC         4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK            5
+#define DISP_CC_MDSS_BYTE1_CLK                 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC             7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC         8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK            9
+#define DISP_CC_MDSS_DP_AUX1_CLK               10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC           11
+#define DISP_CC_MDSS_DP_AUX_CLK                        12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC            13
+#define DISP_CC_MDSS_DP_LINK1_CLK              14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC          15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC      16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK         17
+#define DISP_CC_MDSS_DP_LINK_CLK               18
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC           19
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC       20
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK          21
+#define DISP_CC_MDSS_DP_PIXEL1_CLK             22
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC         23
+#define DISP_CC_MDSS_DP_PIXEL2_CLK             24
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC         25
+#define DISP_CC_MDSS_DP_PIXEL_CLK              26
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC          27
+#define DISP_CC_MDSS_ESC0_CLK                  28
+#define DISP_CC_MDSS_ESC0_CLK_SRC              29
+#define DISP_CC_MDSS_ESC1_CLK                  30
+#define DISP_CC_MDSS_ESC1_CLK_SRC              31
+#define DISP_CC_MDSS_MDP_CLK                   32
+#define DISP_CC_MDSS_MDP_CLK_SRC               33
+#define DISP_CC_MDSS_MDP_LUT_CLK               34
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK          35
+#define DISP_CC_MDSS_PCLK0_CLK                 36
+#define DISP_CC_MDSS_PCLK0_CLK_SRC             37
+#define DISP_CC_MDSS_PCLK1_CLK                 38
+#define DISP_CC_MDSS_PCLK1_CLK_SRC             39
+#define DISP_CC_MDSS_ROT_CLK                   40
+#define DISP_CC_MDSS_ROT_CLK_SRC               41
+#define DISP_CC_MDSS_RSCC_AHB_CLK              42
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK            43
+#define DISP_CC_MDSS_VSYNC_CLK                 44
+#define DISP_CC_MDSS_VSYNC_CLK_SRC             45
+#define DISP_CC_PLL0                           46
+#define DISP_CC_PLL1                           47
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR                  0
+#define DISP_CC_MDSS_RSCC_BCR                  1
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC                              0
+
+#endif