drm/amd/pm: decouple the watermark table setting from socclk/uclk dpms

As they have no real dependence. And for Navi1x, the socclk/uclk dpms
are enabled after DAL initialization.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3612841d40dc9984931c834cc675e18b23d5661c..7859f1911a7233f9733b186b2f15b4db1fd6c743 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1818,17 +1818,16 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
        if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
                return -EOPNOTSUPP;
 
+       if (smu->disable_watermark)
+               return 0;
+
        mutex_lock(&smu->mutex);
 
-       if (!smu->disable_watermark &&
-                       smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
-                       smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
-               ret = smu_set_watermarks_table(smu, clock_ranges);
+       ret = smu_set_watermarks_table(smu, clock_ranges);
 
-               if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
-                       smu->watermarks_bitmap |= WATERMARKS_EXIST;
-                       smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
-               }
+       if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
+               smu->watermarks_bitmap |= WATERMARKS_EXIST;
+               smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
        }
 
        mutex_unlock(&smu->mutex);