drm/i915/icl: Do not change reserved registers related to PSR2

For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
unset in gen10 + GLK we can just drop it and fix for both gens.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-5-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e463bef3c804896cb5dd4ce1318dbe2a2f880b54..b513a15d60e1989a75ae96b99a5c84ea5a8069f7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -649,17 +649,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                hsw_psr_setup_aux(intel_dp);
 
-       if (dev_priv->psr.psr2_enabled) {
+       if (dev_priv->psr.psr2_enabled && (IS_GEN9(dev_priv) &&
+                                          !IS_GEMINILAKE(dev_priv))) {
                i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
                                                        cpu_transcoder);
                u32 chicken = I915_READ(reg);
 
-               if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
-                       chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
-                                  | PSR2_ADD_VERTICAL_LINE_COUNT);
-
-               else
-                       chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
+               chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
+                          PSR2_ADD_VERTICAL_LINE_COUNT;
                I915_WRITE(reg, chicken);
        }