drm/i915/cnl: WaDisableEnhancedSBEVertexCaching

WA forTDS handle reallocation getting dropped by SDE,
which may result in PS attribute corruption.

Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset.

v2: Make it until B0 as spec tells. (by Mika).

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index e66817d5d4adccaa468b542920399ebd3bcc0112..d23f1887430943b3ef97f587fde73b6459409f39 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1074,6 +1074,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
        WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
                          GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
+       /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
+       if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
+               WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+                                 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
+
        /* WaInPlaceDecompressionHang:cnl */
        WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);