The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@
12170000
2. i2c-9/i2c@38
The first node represents the actual SATA PHY device with phy-cells.
The second represents an additional I2C interface, needed by the driver
to communicate with the SATA PHY device. It is not a PHY-provider in
the terms of dtschema so rename it to silence dtbs_check warning:
arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml
This second device node is also a property of SoC, not a board so move
it there.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200902155733.20271-2-krzk@kernel.org
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
-
- sata_phy_i2c: sata-phy@38 {
- compatible = "samsung,exynos-sataphy-i2c";
- reg = <0x38>;
- };
};
&i2s0 {
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
+&sata_phy_i2c {
+ status = "okay";
+};
+
&soc {
/*
* For unknown reasons HDMI-DDC does not work with Exynos I2C
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
-
- sata_phy_i2c: sata-phy@38 {
- compatible = "samsung,exynos-sataphy-i2c";
- reg = <0x38>;
- };
};
&i2s0 {
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
+&sata_phy_i2c {
+ status = "okay";
+};
+
&spi_1 {
status = "okay";
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
clocks = <&clock CLK_SATA_PHYI2C>;
clock-names = "i2c";
status = "disabled";
+
+ sata_phy_i2c: sata-phy-i2c@38 {
+ compatible = "samsung,exynos-sataphy-i2c";
+ reg = <0x38>;
+ status = "disabled";
+ };
};
spi_0: spi@12d20000 {