{
struct drm_i915_private *dev_priv = to_i915(dev);
- I915_WRITE(HWSTAM, 0xffffffff);
+ if (IS_GEN5(dev_priv))
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET(DE);
if (IS_GEN7(dev_priv))
dev_priv->irq_mask = ~display_mask;
- I915_WRITE(HWSTAM, 0xeffe);
-
ibx_irq_pre_postinstall(dev);
GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
gen5_gt_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffffff);
-
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
i9xx_pipestat_irq_reset(dev_priv);
+ I915_WRITE16(HWSTAM, 0xffff);
+
GEN2_IRQ_RESET();
}
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xffffeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}
i9xx_pipestat_irq_reset(dev_priv);
- I915_WRITE(HWSTAM, 0xeffe);
+ I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}