drm/i915: get a runtime PM ref for debugfs entries where needed

These debugfs entries access registers that need the D0 power state so
get an RPM ref for them.

v2:
- for all these entries we only need D0 state, so get only an RPM ref,
  not a power domain ref (Daniel, Paulo)
- the dpio entry is not an issue any more as it got removed (Ville)
- restore commit message from v1 (Paulo)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4c785a26dcebb8d10f4af53bd231aef65d10ab16..cad175c325c265e57bb4a0afc4ed668092839945 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1239,9 +1239,13 @@ static int vlv_drpc_info(struct seq_file *m)
        u32 rpmodectl1, rcctl1;
        unsigned fw_rendercount = 0, fw_mediacount = 0;
 
+       intel_runtime_pm_get(dev_priv);
+
        rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
        rcctl1 = I915_READ(GEN6_RC_CONTROL);
 
+       intel_runtime_pm_put(dev_priv);
+
        seq_printf(m, "Video Turbo Mode: %s\n",
                   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
        seq_printf(m, "Turbo enabled: %s\n",
@@ -3257,9 +3261,15 @@ static int
 i915_wedged_set(void *data, u64 val)
 {
        struct drm_device *dev = data;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       intel_runtime_pm_get(dev_priv);
 
        i915_handle_error(dev, val,
                          "Manually setting wedged to %llu", val);
+
+       intel_runtime_pm_put(dev_priv);
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 9c57029f6f4b4b9ba6b63ce2493eac4942f5eb59..3620997e43f50bd3089f760cc2a50e374a6fd502 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -263,6 +263,8 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 
        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 
+       intel_runtime_pm_get(dev_priv);
+
        mutex_lock(&dev_priv->rps.hw_lock);
        if (IS_VALLEYVIEW(dev_priv->dev)) {
                u32 freq;
@@ -273,6 +275,8 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
        }
        mutex_unlock(&dev_priv->rps.hw_lock);
 
+       intel_runtime_pm_put(dev_priv);
+
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 }