Add support for the arm breakpoint syscall

OABI arm used a software interrupt(0xef9f0001) for breakpoints.
Since 2005 gdb has used the break instruction(0xe7f001f0) for EABI.
Apparently Steel Bank Common Lisp still uses the swi instruction.

This is the kernel implementation:
http://lxr.free-electrons.com/source/arch/arm/kernel/traps.c#L598

Signed-off-by: Hunter Laux <hunterlaux@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

diff --git a/linux-user/arm/syscall.h b/linux-user/arm/syscall.h
index ce2c2a8ed0931efbe7e35091e62f1a893a282d4a..e0d2cc3e5d1940e48000915a6a117dc35dc14b5d 100644 (file)
--- a/linux-user/arm/syscall.h
+++ b/linux-user/arm/syscall.h
@@ -29,6 +29,7 @@ struct target_pt_regs {
 #define ARM_THUMB_SYSCALL      0
 
 #define ARM_NR_BASE      0xf0000
+#define ARM_NR_breakpoint (ARM_NR_BASE + 1)
 #define ARM_NR_cacheflush (ARM_NR_BASE + 2)
 #define ARM_NR_set_tls   (ARM_NR_BASE + 5)
 

diff --git a/linux-user/main.c b/linux-user/main.c
index df1bb0e758a3dccf15e7062628e552f07cc7e5aa..900a17fa33b2f241a45398e7e59a242f3e8d204a 100644 (file)
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -806,6 +806,9 @@ void cpu_loop(CPUARMState *env)
                             cpu_set_tls(env, env->regs[0]);
                             env->regs[0] = 0;
                             break;
+                        case ARM_NR_breakpoint:
+                            env->regs[15] -= env->thumb ? 2 : 4;
+                            goto excp_debug;
                         default:
                             gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
                                      n);
@@ -849,6 +852,7 @@ void cpu_loop(CPUARMState *env)
             }
             break;
         case EXCP_DEBUG:
+        excp_debug:
             {
                 int sig;