static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
{
.phys_base = OMAP730_MCBSP1_BASE,
- .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_730_McBSP1RX,
},
{
.phys_base = OMAP730_MCBSP2_BASE,
- .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_730_McBSP2RX,
static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
{
.phys_base = OMAP1510_MCBSP1_BASE,
- .virt_base = OMAP1510_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_McBSP1RX,
},
{
.phys_base = OMAP1510_MCBSP2_BASE,
- .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
.rx_irq = INT_1510_SPI_RX,
},
{
.phys_base = OMAP1510_MCBSP3_BASE,
- .virt_base = OMAP1510_MCBSP3_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_McBSP3RX,
static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
{
.phys_base = OMAP1610_MCBSP1_BASE,
- .virt_base = OMAP1610_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_McBSP1RX,
},
{
.phys_base = OMAP1610_MCBSP2_BASE,
- .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
.rx_irq = INT_1610_McBSP2_RX,
},
{
.phys_base = OMAP1610_MCBSP3_BASE,
- .virt_base = OMAP1610_MCBSP3_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_McBSP3RX,
static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
{
.phys_base = OMAP24XX_MCBSP1_BASE,
- .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
},
{
.phys_base = OMAP24XX_MCBSP2_BASE,
- .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
{
.phys_base = OMAP34XX_MCBSP1_BASE,
- .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
},
{
.phys_base = OMAP34XX_MCBSP2_BASE,
- .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
struct omap_mcbsp_platform_data {
unsigned long phys_base;
- u32 virt_base;
u8 dma_rx_sync, dma_tx_sync;
u16 rx_irq, tx_irq;
struct omap_mcbsp_ops *ops;
struct omap_mcbsp {
struct device *dev;
unsigned long phys_base;
- u32 io_base;
+ void __iomem *io_base;
u8 id;
u8 free;
omap_mcbsp_word_length rx_word_length;
*/
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
{
- u32 io_base;
+ void __iomem *io_base;
if (!omap_mcbsp_check_valid_id(id)) {
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
}
io_base = mcbsp[id].io_base;
- dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n",
- mcbsp[id].id, io_base);
+ dev_dbg(mcbsp[id].dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
+ mcbsp[id].id, mcbsp[id].phys_base);
/* We write the given config */
OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
*/
void omap_mcbsp_start(unsigned int id)
{
- u32 io_base;
+ void __iomem *io_base;
u16 w;
if (!omap_mcbsp_check_valid_id(id)) {
void omap_mcbsp_stop(unsigned int id)
{
- u32 io_base;
+ void __iomem *io_base;
u16 w;
if (!omap_mcbsp_check_valid_id(id)) {
/* polled mcbsp i/o operations */
int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
{
- u32 base;
+ void __iomem *base;
if (!omap_mcbsp_check_valid_id(id)) {
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
int omap_mcbsp_pollread(unsigned int id, u16 *buf)
{
- u32 base;
+ void __iomem *base;
if (!omap_mcbsp_check_valid_id(id)) {
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
*/
void omap_mcbsp_xmit_word(unsigned int id, u32 word)
{
- u32 io_base;
+ void __iomem *io_base;
omap_mcbsp_word_length word_length;
if (!omap_mcbsp_check_valid_id(id)) {
u32 omap_mcbsp_recv_word(unsigned int id)
{
- u32 io_base;
+ void __iomem *io_base;
u16 word_lsb, word_msb = 0;
omap_mcbsp_word_length word_length;
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
{
- u32 io_base;
+ void __iomem *io_base;
omap_mcbsp_word_length tx_word_length;
omap_mcbsp_word_length rx_word_length;
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
{
- u32 io_base, clock_word = 0;
+ u32 clock_word = 0;
+ void __iomem *io_base;
omap_mcbsp_word_length tx_word_length;
omap_mcbsp_word_length rx_word_length;
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
mcbsp[id].dma_rx_lch = -1;
mcbsp[id].phys_base = pdata->phys_base;
- mcbsp[id].io_base = pdata->virt_base;
+ mcbsp[id].io_base = ioremap(pdata->phys_base, SZ_4K);
+ if (!mcbsp[id].io_base) {
+ ret = -ENOMEM;
+ goto err_ioremap;
+ }
+
/* Default I/O is IRQ based */
mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
mcbsp[id].tx_irq = pdata->tx_irq;
if (pdata->clk_name)
mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
if (IS_ERR(mcbsp[id].clk)) {
- mcbsp[id].free = 0;
dev_err(&pdev->dev,
"Invalid clock configuration for McBSP%d.\n",
mcbsp[id].id);
- ret = -EINVAL;
- goto exit;
+ ret = PTR_ERR(mcbsp[id].clk);
+ goto err_clk;
}
mcbsp[id].pdata = pdata;
mcbsp[id].dev = &pdev->dev;
platform_set_drvdata(pdev, &mcbsp[id]);
+ return 0;
+err_clk:
+ iounmap(mcbsp[id].io_base);
+err_ioremap:
+ mcbsp[id].free = 0;
exit:
return ret;
}
clk_disable(mcbsp->clk);
clk_put(mcbsp->clk);
+ iounmap(mcbsp->io_base);
+
mcbsp->clk = NULL;
mcbsp->free = 0;
mcbsp->dev = NULL;