arm: mvebu: Add support for SPI controller in Armada 370/XP

The Armada 370 and Armada XP SoC has an SPI controller.
This patch adds support for this controller in Armada 370
and Armada XP SoC common device tree files.

Note that the Armada XP SPI register length is 0x50 bytes,
while Armada 370 SPI register length is 0x28 bytes,
so we choose the smaller of the two.

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index cb434b2de6280a00e746135bba042820ebd8114f..6f1acc75e1559ca109066c7ad68c6e11f50087a0 100644 (file)
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -161,6 +161,27 @@
                        status = "disabled";
                };
 
+               spi0: spi@d0010600 {
+                       compatible = "marvell,orion-spi";
+                       reg = <0xd0010600 0x28>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       interrupts = <30>;
+                       clocks = <&coreclk 0>;
+                       status = "disabled";
+               };
+
+               spi1: spi@d0010680 {
+                       compatible = "marvell,orion-spi";
+                       reg = <0xd0010680 0x28>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       interrupts = <92>;
+                       clocks = <&coreclk 0>;
+                       status = "disabled";
+               };
        };
 };