drm/amdgpu: Make display watermark calculations more accurate

Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.

Implemented here for DCE 6,8,10,11.
Successfully tested on DCE 10 with AMD R9 380 Tonga.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f525ae4e057627617d94863998f4fb1d423efffa..67e7d8ee1aab29f2214e6a3dcc62151a368bd6ba 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1214,14 +1214,14 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce10_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1236,7 +1236,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1275,7 +1275,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 3eac27f24d9424c4f959b6286f7d4d5f08a4b0c7..7a91afba019861acd8b119c5f1a99569b00041d0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1183,14 +1183,14 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce10_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1205,7 +1205,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1244,7 +1244,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 838cf1a778f2f034b4e5964108794f6c3a1a5074..b20cc07eea6446ff31eaf031554db037b24cb579 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -986,7 +986,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce6_wm_params wm_low, wm_high;
        u32 dram_channels;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -996,8 +996,8 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
        fixed20_12 a, b, c;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
                priority_a_cnt = 0;
                priority_b_cnt = 0;
 
@@ -1016,7 +1016,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1043,7 +1043,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 1b0717b11efeac78914c52f7c40688c458e2bca9..b420051e9da463722e2f266b85b856a01ad8de2b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1098,14 +1098,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce8_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1120,7 +1120,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1159,7 +1159,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)