drm/i915: set FDI_RX_MISC to recommended values on CPT/PPT

My machine here has the correct ones already, but better safe
than sorry. IBX has different settings for that register, and
on IBX the device defaults match the recommended values. Hence
I did not add the respective writes for IBX.

LPT needs the same settings, but that has been done already

commit 4acf518626cdad5bbf7aac9869bd4accbbfb4ad3
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date:   Wed Jul 4 20:15:16 2012 -0300

    drm/i915: program FDI_RX TP and FDI delays

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 612b4105b758c21e55e84d89e26275ca5650ca55..a3e715b4290de111c85340b333f8f189c0a09d71 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2479,6 +2479,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);
 
+       I915_WRITE(FDI_RX_MISC(pipe),
+                  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
+
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
@@ -2611,6 +2614,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
        temp |= FDI_COMPOSITE_SYNC;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);
 
+       I915_WRITE(FDI_RX_MISC(pipe),
+                  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
+
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_AUTO;