QTAILQ_FOREACH(block, &ram_list.blocks, next) {
if (!strncmp(id, block->idstr, sizeof(id))) {
if (block->length != length) {
- fprintf(stderr, "Length mismatch: %s: %ld "
- "in != " RAM_ADDR_FMT "\n", id, length,
+ fprintf(stderr,
+ "Length mismatch: %s: " RAM_ADDR_FMT
+ " in != " RAM_ADDR_FMT "\n", id, length,
block->length);
ret = -EINVAL;
goto done;
void cpu_loop(CPUSPARCState *env)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
int trapnr, ret, syscall_nr;
//target_siginfo_t info;
badtrap:
#endif
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
static CPUArchState *next_cpu;
-static bool cpu_thread_is_idle(CPUArchState *env)
+static bool cpu_thread_is_idle(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
if (cpu->stop || cpu->queued_work_first) {
return false;
}
CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
- if (!cpu_thread_is_idle(env)) {
+ if (!cpu_thread_is_idle(ENV_GET_CPU(env))) {
return false;
}
}
for (env = first_cpu; env != NULL; env = env->next_cpu) {
cpu = ENV_GET_CPU(env);
fprintf(stderr, "CPU #%d:\n", cpu->cpu_index);
- cpu_dump_state(env, stderr, fprintf, CPU_DUMP_FPU);
+ cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU);
}
va_end(ap);
abort();
void cpu_synchronize_all_states(void)
{
- CPUArchState *cpu;
+ CPUArchState *env;
- for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
- cpu_synchronize_state(cpu);
+ for (env = first_cpu; env; env = env->next_cpu) {
+ cpu_synchronize_state(ENV_GET_CPU(env));
}
}
return true;
}
-static void cpu_handle_guest_debug(CPUArchState *env)
+static void cpu_handle_guest_debug(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
- gdb_set_stop_cpu(env);
+ gdb_set_stop_cpu(cpu);
qemu_system_debug_request();
cpu->stopped = true;
}
static void cpu_signal(int sig)
{
if (cpu_single_env) {
- cpu_exit(cpu_single_env);
+ cpu_exit(ENV_GET_CPU(cpu_single_env));
}
exit_request = 1;
}
{
}
-static void qemu_kvm_init_cpu_signals(CPUArchState *env)
+static void qemu_kvm_init_cpu_signals(CPUState *cpu)
{
int r;
sigset_t set;
pthread_sigmask(SIG_BLOCK, NULL, &set);
sigdelset(&set, SIG_IPI);
sigdelset(&set, SIGBUS);
- r = kvm_set_signal_mask(env, &set);
+ r = kvm_set_signal_mask(cpu, &set);
if (r) {
fprintf(stderr, "kvm_set_signal_mask: %s\n", strerror(-r));
exit(1);
}
#else /* _WIN32 */
-static void qemu_kvm_init_cpu_signals(CPUArchState *env)
+static void qemu_kvm_init_cpu_signals(CPUState *cpu)
{
abort();
}
}
}
-static void qemu_kvm_wait_io_event(CPUArchState *env)
+static void qemu_kvm_wait_io_event(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
- while (cpu_thread_is_idle(env)) {
+ while (cpu_thread_is_idle(cpu)) {
qemu_cond_wait(cpu->halt_cond, &qemu_global_mutex);
}
static void *qemu_kvm_cpu_thread_fn(void *arg)
{
- CPUArchState *env = arg;
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = arg;
int r;
qemu_mutex_lock(&qemu_global_mutex);
qemu_thread_get_self(cpu->thread);
cpu->thread_id = qemu_get_thread_id();
- cpu_single_env = env;
+ cpu_single_env = cpu->env_ptr;
r = kvm_init_vcpu(cpu);
if (r < 0) {
exit(1);
}
- qemu_kvm_init_cpu_signals(env);
+ qemu_kvm_init_cpu_signals(cpu);
/* signal CPU creation */
cpu->created = true;
while (1) {
if (cpu_can_run(cpu)) {
- r = kvm_cpu_exec(env);
+ r = kvm_cpu_exec(cpu);
if (r == EXCP_DEBUG) {
- cpu_handle_guest_debug(env);
+ cpu_handle_guest_debug(cpu);
}
}
- qemu_kvm_wait_io_event(env);
+ qemu_kvm_wait_io_event(cpu);
}
return NULL;
fprintf(stderr, "qtest is not supported under Windows\n");
exit(1);
#else
- CPUArchState *env = arg;
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = arg;
sigset_t waitset;
int r;
cpu->created = true;
qemu_cond_signal(&qemu_cpu_cond);
- cpu_single_env = env;
+ cpu_single_env = cpu->env_ptr;
while (1) {
cpu_single_env = NULL;
qemu_mutex_unlock_iothread();
exit(1);
}
qemu_mutex_lock_iothread();
- cpu_single_env = env;
+ cpu_single_env = cpu->env_ptr;
qemu_wait_io_event_common(cpu);
}
}
}
-static void qemu_kvm_start_vcpu(CPUArchState *env)
+static void qemu_kvm_start_vcpu(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
cpu->thread = g_malloc0(sizeof(QemuThread));
cpu->halt_cond = g_malloc0(sizeof(QemuCond));
qemu_cond_init(cpu->halt_cond);
- qemu_thread_create(cpu->thread, qemu_kvm_cpu_thread_fn, env,
+ qemu_thread_create(cpu->thread, qemu_kvm_cpu_thread_fn, cpu,
QEMU_THREAD_JOINABLE);
while (!cpu->created) {
qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex);
}
}
-static void qemu_dummy_start_vcpu(CPUArchState *env)
+static void qemu_dummy_start_vcpu(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
cpu->thread = g_malloc0(sizeof(QemuThread));
cpu->halt_cond = g_malloc0(sizeof(QemuCond));
qemu_cond_init(cpu->halt_cond);
- qemu_thread_create(cpu->thread, qemu_dummy_cpu_thread_fn, env,
+ qemu_thread_create(cpu->thread, qemu_dummy_cpu_thread_fn, cpu,
QEMU_THREAD_JOINABLE);
while (!cpu->created) {
qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex);
}
}
-void qemu_init_vcpu(void *_env)
+void qemu_init_vcpu(CPUState *cpu)
{
- CPUArchState *env = _env;
- CPUState *cpu = ENV_GET_CPU(env);
-
cpu->nr_cores = smp_cores;
cpu->nr_threads = smp_threads;
cpu->stopped = true;
if (kvm_enabled()) {
- qemu_kvm_start_vcpu(env);
+ qemu_kvm_start_vcpu(cpu);
} else if (tcg_enabled()) {
qemu_tcg_init_vcpu(cpu);
} else {
- qemu_dummy_start_vcpu(env);
+ qemu_dummy_start_vcpu(cpu);
}
}
CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
cpu_single_cpu->stop = false;
cpu_single_cpu->stopped = true;
- cpu_exit(cpu_single_env);
+ cpu_exit(cpu_single_cpu);
qemu_cond_signal(&qemu_pause_cond);
}
}
if (cpu_can_run(cpu)) {
r = tcg_cpu_exec(env);
if (r == EXCP_DEBUG) {
- cpu_handle_guest_debug(env);
+ cpu_handle_guest_debug(cpu);
break;
}
} else if (cpu->stop || cpu->stopped) {
CPUState *cpu = ENV_GET_CPU(env);
CpuInfoList *info;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cpu);
info = g_malloc0(sizeof(*info));
info->value = g_malloc0(sizeof(*info->value));
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
mr = iotlb_to_region(pd);
if (memory_region_is_unassigned(mr)) {
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
- cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
-#else
- cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
- TARGET_FMT_lx "\n", addr);
-#endif
+ CPUState *cpu = ENV_GET_CPU(env1);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->do_unassigned_access) {
+ cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
+ } else {
+ cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
+ TARGET_FMT_lx "\n", addr);
+ }
}
p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
return qemu_ram_addr_from_host_nofail(p);
return 0;
}
-static const VMStateDescription vmstate_cpu_common = {
+const VMStateDescription vmstate_cpu_common = {
.name = "cpu_common",
.version_id = 1,
.minimum_version_id = 1,
VMSTATE_END_OF_LIST()
}
};
-#else
-#define vmstate_cpu_common vmstate_dummy
+
#endif
CPUState *qemu_get_cpu(int index)
#endif
}
-void cpu_exit(CPUArchState *env)
-{
- CPUState *cpu = ENV_GET_CPU(env);
-
- cpu->exit_request = 1;
- cpu->tcg_exit_req = 1;
-}
-
void cpu_abort(CPUArchState *env, const char *fmt, ...)
{
+ CPUState *cpu = ENV_GET_CPU(env);
va_list ap;
va_list ap2;
fprintf(stderr, "qemu: fatal: ");
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
- cpu_dump_state(env, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
+ cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
if (qemu_log_enabled()) {
qemu_log("qemu: fatal: ");
qemu_log_vprintf(fmt, ap2);
static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
{
- cpu_synchronize_state(s->c_cpu);
+ cpu_synchronize_state(ENV_GET_CPU(s->c_cpu));
#if defined(TARGET_I386)
s->c_cpu->eip = pc;
#elif defined (TARGET_PPC)
static CPUArchState *find_cpu(uint32_t thread_id)
{
- CPUArchState *env;
CPUState *cpu;
- for (env = first_cpu; env != NULL; env = env->next_cpu) {
- cpu = ENV_GET_CPU(env);
- if (cpu_index(cpu) == thread_id) {
- return env;
- }
+ cpu = qemu_get_cpu(thread_id);
+ if (cpu == NULL) {
+ return NULL;
}
-
- return NULL;
+ return cpu->env_ptr;
}
static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
break;
case 'g':
- cpu_synchronize_state(s->g_cpu);
+ cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
env = s->g_cpu;
len = 0;
for (addr = 0; addr < num_g_regs; addr++) {
put_packet(s, buf);
break;
case 'G':
- cpu_synchronize_state(s->g_cpu);
+ cpu_synchronize_state(ENV_GET_CPU(s->g_cpu));
env = s->g_cpu;
registers = mem_buf;
len = strlen(p) / 2;
env = find_cpu(thread);
if (env != NULL) {
CPUState *cpu = ENV_GET_CPU(env);
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cpu);
len = snprintf((char *)mem_buf, sizeof(mem_buf),
"CPU#%d [%s]", cpu->cpu_index,
cpu->halted ? "halted " : "running");
return RS_IDLE;
}
-void gdb_set_stop_cpu(CPUArchState *env)
+void gdb_set_stop_cpu(CPUState *cpu)
{
+ CPUArchState *env = cpu->env_ptr;
+
gdbserver_state->c_cpu = env;
gdbserver_state->g_cpu = env;
}
is still in the running state, which can cause packets to be dropped
and state transition 'T' packets to be sent while the syscall is still
being processed. */
- cpu_exit(s->c_cpu);
+ cpu_exit(ENV_GET_CPU(s->c_cpu));
#endif
}
break;
default:
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
+ cpu = CPU(alpha_env_get_cpu(cpu_single_env));
+ cpu_unassigned_access(cpu, addr, false, false, 0, size);
return -1;
}
static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
{
TyphoonState *s = opaque;
+ CPUState *cs;
uint64_t ret = 0;
if (addr & 4) {
break;
default:
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
+ cs = CPU(alpha_env_get_cpu(cpu_single_env));
+ cpu_unassigned_access(cs, addr, false, false, 0, size);
return -1;
}
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
+ CPUState *cpu_single_cpu = CPU(alpha_env_get_cpu(cpu_single_env));
uint64_t val, oldval, newval;
if (addr & 4) {
break;
default:
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
+ cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size);
return;
}
}
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
+ CPUState *cs;
uint64_t val, oldval;
if (addr & 4) {
break;
default:
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
+ cs = CPU(alpha_env_get_cpu(cpu_single_env));
+ cpu_unassigned_access(cs, addr, true, false, 0, size);
return;
}
}
uint32_t lvt;
int ret;
- cpu_synchronize_state(&s->cpu->env);
+ cpu_synchronize_state(cpu);
lvt = s->lvt[APIC_LVT_LINT1];
if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cs);
if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
if (s->state == VAPIC_ACTIVE) {
hwaddr rom_paddr;
VAPICROMState *s = opaque;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(x86_env_get_cpu(env)));
/*
* The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
| MULTIBOOT_FLAGS_CMDLINE
| MULTIBOOT_FLAGS_MODULES
| MULTIBOOT_FLAGS_MMAP);
- stl_p(bootinfo + MBI_MEM_LOWER, 640);
- stl_p(bootinfo + MBI_MEM_UPPER, (ram_size / 1024) - 1024);
stl_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */
stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP);
CPUX86State *env = cpu_single_env;
if (env && level) {
- cpu_exit(env);
+ cpu_exit(CPU(x86_env_get_cpu(env)));
}
}
CPUMIPSState *env = cpu_single_env;
if (env && level) {
- cpu_exit(env);
+ cpu_exit(CPU(mips_env_get_cpu(env)));
}
}
CPUMIPSState *env = cpu_single_env;
if (env && level) {
- cpu_exit(env);
+ cpu_exit(CPU(mips_env_get_cpu(env)));
}
}
CPUMIPSState *env = cpu_single_env;
if (env && level) {
- cpu_exit(env);
+ cpu_exit(CPU(mips_env_get_cpu(env)));
}
}
unsigned char command;
uint32_t eax;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(x86_env_get_cpu(env)));
eax = env->regs[R_EAX];
if (eax != VMPORT_MAGIC)
hwaddr map_size = 64 * 1024 * 1024;
hwaddr map_start;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cpu);
stl_p(&curspin->pir, env->spr[SPR_PIR]);
env->nip = ldq_p(&curspin->addr) & (map_size - 1);
env->gpr[3] = ldq_p(&curspin->r3);
CPUPPCState *env = cpu_single_env;
if (env && level) {
- cpu_exit(env);
+ cpu_exit(CPU(ppc_env_get_cpu(env)));
}
}
/* This will make sure qemu state is up to date with kvm, and
* mark it dirty so our changes get flushed back before the
* new cpu enters */
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
env->nip = start;
CPUArchState *cpu_copy(CPUArchState *env);
-#define CPU_DUMP_CODE 0x00010000
-#define CPU_DUMP_FPU 0x00020000 /* dump FPU register state, not just integer */
-/* dump info about TCG QEMU's condition code optimization state */
-#define CPU_DUMP_CCOP 0x00040000
-
-void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags);
-void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags);
-
void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
extern CPUArchState *first_cpu;
| CPU_INTERRUPT_TGT_EXT_3 \
| CPU_INTERRUPT_TGT_EXT_4)
-void cpu_exit(CPUArchState *s);
-
/* Breakpoint/watchpoint flags */
#define BP_MEM_READ 0x01
#define BP_MEM_WRITE 0x02
/* CPU interfaces that are target independent. */
+#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
+#endif
#ifndef NEED_CPU_H
#include "exec/poison.h"
#include <inttypes.h>
#include "qemu/osdep.h"
#include "qemu/queue.h"
+#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
+#endif
#ifndef TARGET_LONG_BITS
#error TARGET_LONG_BITS must be defined before including this header
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
int use_gdb_syscalls(void);
-void gdb_set_stop_cpu(CPUArchState *env);
+void gdb_set_stop_cpu(CPUState *cpu);
void gdb_exit(CPUArchState *, int);
#ifdef CONFIG_USER_ONLY
int gdb_queuesig (void);
#ifndef HWADDR_H
#define HWADDR_H
-#ifndef CONFIG_USER_ONLY
-
#define HWADDR_BITS 64
/* hwaddr is the type of a physical address (its size can
be different from 'target_ulong'). */
#define HWADDR_PRIX PRIX64
#endif
-
-#endif
#include <stdbool.h>
#include "qemu-common.h"
#include "exec/cpu-common.h"
+#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
+#endif
#include "qemu/queue.h"
#include "exec/iorange.h"
#include "exec/ioport.h"
void cpu_exec_init_all(void);
/* CPU save/load. */
+#ifdef CPU_SAVE_VERSION
void cpu_save(QEMUFile *f, void *opaque);
int cpu_load(QEMUFile *f, void *opaque, int version_id);
+#endif
/* Unblock cpu */
void qemu_cpu_kick_self(void);
int done;
};
-#ifdef CONFIG_USER_ONLY
-static inline void qemu_init_vcpu(void *env)
-{
-}
-#else
-void qemu_init_vcpu(void *env);
-#endif
-
/**
* Sends a (part of) iovec down a socket, yielding when the socket is full, or
static inline void log_cpu_state(CPUArchState *env1, int flags)
{
if (qemu_log_enabled()) {
- cpu_dump_state(env1, qemu_logfile, fprintf, flags);
+ cpu_dump_state(ENV_GET_CPU(env1), qemu_logfile, fprintf, flags);
}
}
#include <signal.h>
#include "hw/qdev-core.h"
+#include "exec/hwaddr.h"
#include "qemu/thread.h"
#include "qemu/typedefs.h"
typedef struct CPUState CPUState;
+typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec, int opaque,
+ unsigned size);
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
* instantiatable CPU type.
* @reset: Callback to reset the #CPUState to its initial state.
* @do_interrupt: Callback for interrupt handling.
+ * @do_unassigned_access: Callback for unassigned access handling.
+ * @dump_state: Callback for dumping state.
+ * @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
void (*reset)(CPUState *cpu);
void (*do_interrupt)(CPUState *cpu);
+ CPUUnassignedAccess do_unassigned_access;
+ void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+ void (*dump_statistics)(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
+/**
+ * CPUDumpFlags:
+ * @CPU_DUMP_CODE:
+ * @CPU_DUMP_FPU: dump FPU register state, not just integer
+ * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
+ */
+enum CPUDumpFlags {
+ CPU_DUMP_CODE = 0x00010000,
+ CPU_DUMP_FPU = 0x00020000,
+ CPU_DUMP_CCOP = 0x00040000,
+};
+
+/**
+ * cpu_dump_state:
+ * @cpu: The CPU whose state is to be dumped.
+ * @f: File to dump to.
+ * @cpu_fprintf: Function to dump with.
+ * @flags: Flags what to dump.
+ *
+ * Dumps CPU state.
+ */
+void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
+/**
+ * cpu_dump_statistics:
+ * @cpu: The CPU whose state is to be dumped.
+ * @f: File to dump to.
+ * @cpu_fprintf: Function to dump with.
+ * @flags: Flags what to dump.
+ *
+ * Dumps CPU statistics.
+ */
+void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
/**
* cpu_reset:
* @cpu: The CPU whose state is to be reset.
*
* The @value argument is intentionally discarded for the non-softmmu targets
* to avoid linker errors or excessive preprocessor usage. If this behavior
- * is undesired, you should assign #CPUState.vmsd directly instead.
+ * is undesired, you should assign #CPUClass.vmsd directly instead.
*/
#ifndef CONFIG_USER_ONLY
static inline void cpu_class_set_vmsd(CPUClass *cc,
#define cpu_class_set_vmsd(cc, value) ((cc)->vmsd = NULL)
#endif
+#ifndef CONFIG_USER_ONLY
+static inline void cpu_class_set_do_unassigned_access(CPUClass *cc,
+ CPUUnassignedAccess value)
+{
+ cc->do_unassigned_access = value;
+}
+#else
+#define cpu_class_set_do_unassigned_access(cc, value) \
+ ((cc)->do_unassigned_access = NULL)
+#endif
+
+/**
+ * device_class_set_vmsd:
+ * @dc: Device class
+ * @value: Value to set. Unused for %CONFIG_USER_ONLY.
+ *
+ * Sets #VMStateDescription for @dc.
+ *
+ * The @value argument is intentionally discarded for the non-softmmu targets
+ * to avoid linker errors or excessive preprocessor usage. If this behavior
+ * is undesired, you should assign #DeviceClass.vmsd directly instead.
+ */
+#ifndef CONFIG_USER_ONLY
+static inline void device_class_set_vmsd(DeviceClass *dc,
+ const struct VMStateDescription *value)
+{
+ dc->vmsd = value;
+}
+#else
+#define device_class_set_vmsd(dc, value) ((dc)->vmsd = NULL)
+#endif
+
/**
* qemu_cpu_has_work:
* @cpu: The vCPU to check.
#endif /* USER_ONLY */
+#ifndef CONFIG_USER_ONLY
+
+static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec,
+ int opaque, unsigned size)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->do_unassigned_access) {
+ cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
+ }
+}
+
+#endif
+
/**
* cpu_reset_interrupt:
* @cpu: The CPU to clear the interrupt on.
*/
void cpu_reset_interrupt(CPUState *cpu, int mask);
+/**
+ * cpu_exit:
+ * @cpu: The CPU to exit.
+ *
+ * Requests the CPU @cpu to exit execution.
+ */
+void cpu_exit(CPUState *cpu);
+
/**
* cpu_resume:
* @cpu: The CPU to resume.
*/
void cpu_resume(CPUState *cpu);
+/**
+ * qemu_init_vcpu:
+ * @cpu: The vCPU to initialize.
+ *
+ * Initializes a vCPU.
+ */
+void qemu_init_vcpu(CPUState *cpu);
+
+#ifdef CONFIG_SOFTMMU
+extern const struct VMStateDescription vmstate_cpu_common;
+#else
+#define vmstate_cpu_common vmstate_dummy
+#endif
+
+#define VMSTATE_CPU() { \
+ .name = "parent_obj", \
+ .size = sizeof(CPUState), \
+ .vmsd = &vmstate_cpu_common, \
+ .flags = VMS_STRUCT, \
+ .offset = 0, \
+}
+
#endif
QemuOpts *qemu_chr_parse_compat(const char *label, const char *filename);
void register_char_driver(const char *name, CharDriverState *(*open)(QemuOpts *));
-void register_char_driver_qapi(const char *name, int kind,
+void register_char_driver_qapi(const char *name, ChardevBackendKind kind,
void (*parse)(QemuOpts *opts, ChardevBackend *backend, Error **errp));
/* add an eventfd to the qemu devices that are polled */
int kvm_has_intx_set_mask(void);
int kvm_init_vcpu(CPUState *cpu);
+int kvm_cpu_exec(CPUState *cpu);
#ifdef NEED_CPU_H
-int kvm_cpu_exec(CPUArchState *env);
#if !defined(CONFIG_USER_ONLY)
void *kvm_ram_alloc(ram_addr_t size);
void kvm_remove_all_breakpoints(CPUArchState *current_env);
int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap);
#ifndef _WIN32
-int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset);
+int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset);
#endif
int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
uint32_t index, int reg);
-void kvm_cpu_synchronize_state(CPUArchState *env);
+void kvm_cpu_synchronize_state(CPUState *cpu);
/* generic hooks - to be moved/refactored once there are more users */
-static inline void cpu_synchronize_state(CPUArchState *env)
+static inline void cpu_synchronize_state(CPUState *cpu)
{
if (kvm_enabled()) {
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cpu);
}
}
}
}
-static int kvm_handle_internal_error(CPUArchState *env, struct kvm_run *run)
+static int kvm_handle_internal_error(CPUState *cpu, struct kvm_run *run)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
fprintf(stderr, "KVM internal error.");
if (kvm_check_extension(kvm_state, KVM_CAP_INTERNAL_ERROR_DATA)) {
int i;
if (run->internal.suberror == KVM_INTERNAL_ERROR_EMULATION) {
fprintf(stderr, "emulation failure\n");
if (!kvm_arch_stop_on_emulation_error(cpu)) {
- cpu_dump_state(env, stderr, fprintf, CPU_DUMP_CODE);
+ cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_CODE);
return EXCP_INTERRUPT;
}
}
}
}
-void kvm_cpu_synchronize_state(CPUArchState *env)
+void kvm_cpu_synchronize_state(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
if (!cpu->kvm_vcpu_dirty) {
run_on_cpu(cpu, do_kvm_cpu_synchronize_state, cpu);
}
cpu->kvm_vcpu_dirty = false;
}
-int kvm_cpu_exec(CPUArchState *env)
+int kvm_cpu_exec(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_run *run = cpu->kvm_run;
int ret, run_ret;
ret = -1;
break;
case KVM_EXIT_INTERNAL_ERROR:
- ret = kvm_handle_internal_error(env, run);
+ ret = kvm_handle_internal_error(cpu, run);
break;
default:
DPRINTF("kvm_arch_handle_exit\n");
} while (ret == 0);
if (ret < 0) {
- cpu_dump_state(env, stderr, fprintf, CPU_DUMP_CODE);
+ cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_CODE);
vm_stop(RUN_STATE_INTERNAL_ERROR);
}
}
#endif /* !KVM_CAP_SET_GUEST_DEBUG */
-int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
+int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset)
{
- CPUState *cpu = ENV_GET_CPU(env);
struct kvm_signal_mask *sigmask;
int r;
{
}
-void kvm_cpu_synchronize_state(CPUArchState *env)
+void kvm_cpu_synchronize_state(CPUState *cpu)
{
}
{
}
-int kvm_cpu_exec(CPUArchState *env)
+int kvm_cpu_exec(CPUState *cpu)
{
- abort ();
+ abort();
}
int kvm_has_sync_mmu(void)
}
#ifndef _WIN32
-int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
+int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset)
{
abort();
}
other_cpu = ENV_GET_CPU(other);
if (other_cpu->running) {
pending_cpus++;
- cpu_exit(other);
+ cpu_exit(other_cpu);
}
}
if (pending_cpus > 1) {
error:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
process_pending_signals(env);
error:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
#endif
void cpu_loop (CPUSPARCState *env)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
int trapnr;
abi_long ret;
target_siginfo_t info;
break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
#define EXCP_DUMP(env, fmt, ...) \
do { \
fprintf(stderr, fmt , ## __VA_ARGS__); \
- cpu_dump_state(env, stderr, fprintf, 0); \
+ cpu_dump_state(ENV_GET_CPU(env), stderr, fprintf, 0); \
qemu_log(fmt, ## __VA_ARGS__); \
if (qemu_log_enabled()) { \
log_cpu_state(env, 0); \
error:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
process_pending_signals(env);
void cpu_loop(CPUOpenRISCState *env)
{
+ CPUState *cs = CPU(openrisc_env_get_cpu(env));
int trapnr, gdbsig;
for (;;) {
break;
case EXCP_DPF:
case EXCP_IPF:
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGSEGV;
break;
case EXCP_TICK:
default:
qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGILL;
break;
}
#ifdef TARGET_SH4
void cpu_loop(CPUSH4State *env)
{
+ CPUState *cs = CPU(sh_env_get_cpu(env));
int trapnr, ret;
target_siginfo_t info;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
#ifdef TARGET_CRIS
void cpu_loop(CPUCRISState *env)
{
+ CPUState *cs = CPU(cris_env_get_cpu(env));
int trapnr, ret;
target_siginfo_t info;
break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
#ifdef TARGET_MICROBLAZE
void cpu_loop(CPUMBState *env)
{
+ CPUState *cs = CPU(mb_env_get_cpu(env));
int trapnr, ret;
target_siginfo_t info;
default:
printf ("Unhandled hw-exception: 0x%x\n",
env->sregs[SR_ESR] & ESR_EC_MASK);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
break;
}
break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
void cpu_loop(CPUM68KState *env)
{
+ CPUState *cs = CPU(m68k_env_get_cpu(env));
int trapnr;
unsigned int n;
target_siginfo_t info;
default:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
process_pending_signals(env);
void cpu_loop(CPUAlphaState *env)
{
+ CPUState *cs = CPU(alpha_env_get_cpu(env));
int trapnr;
target_siginfo_t info;
abi_long sysret;
break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit (1);
}
process_pending_signals (env);
#ifdef TARGET_S390X
void cpu_loop(CPUS390XState *env)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
int trapnr, n, sig;
target_siginfo_t info;
target_ulong addr;
default:
fprintf(stderr, "Unhandled program exception: %#x\n", n);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit(1);
}
break;
default:
fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
exit(1);
}
process_pending_signals (env);
host_to_target_siginfo_noswap(&tinfo, info);
if (queue_signal(thread_env, sig, &tinfo) == 1) {
/* interrupt the virtual CPU as soon as possible */
- cpu_exit(thread_env);
+ cpu_exit(ENV_GET_CPU(thread_env));
}
}
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
-#endif
+ if (cpu_single_env != NULL) {
+ cpu_unassigned_access(ENV_GET_CPU(cpu_single_env),
+ addr, false, false, 0, size);
+ }
return 0;
}
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
-#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
- cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
-#endif
+ if (cpu_single_env != NULL) {
+ cpu_unassigned_access(ENV_GET_CPU(cpu_single_env),
+ addr, true, false, 0, size);
+ }
}
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
QString *outbuf;
ReadLineState *rs;
MonitorControl *mc;
- CPUArchState *mon_cpu;
+ CPUState *mon_cpu;
BlockDriverCompletionFunc *password_completion_cb;
void *password_opaque;
QError *error;
if (cpu == NULL) {
return -1;
}
- cur_mon->mon_cpu = cpu->env_ptr;
+ cur_mon->mon_cpu = cpu;
return 0;
}
monitor_set_cpu(0);
}
cpu_synchronize_state(cur_mon->mon_cpu);
- return cur_mon->mon_cpu;
+ return cur_mon->mon_cpu->env_ptr;
}
int monitor_get_cpu_index(void)
static void do_info_registers(Monitor *mon, const QDict *qdict)
{
+ CPUState *cpu;
CPUArchState *env;
env = mon_get_cpu();
- cpu_dump_state(env, (FILE *)mon, monitor_fprintf, CPU_DUMP_FPU);
+ cpu = ENV_GET_CPU(env);
+ cpu_dump_state(cpu, (FILE *)mon, monitor_fprintf, CPU_DUMP_FPU);
}
static void do_info_jit(Monitor *mon, const QDict *qdict)
}
}
-#if defined(TARGET_PPC)
-/* XXX: not implemented in other targets */
static void do_info_cpu_stats(Monitor *mon, const QDict *qdict)
{
+ CPUState *cpu;
CPUArchState *env;
env = mon_get_cpu();
- cpu_dump_statistics(env, (FILE *)mon, &monitor_fprintf, 0);
+ cpu = ENV_GET_CPU(env);
+ cpu_dump_statistics(cpu, (FILE *)mon, &monitor_fprintf, 0);
}
-#endif
static void do_trace_print_events(Monitor *mon, const QDict *qdict)
{
.help = "show the current VM UUID",
.mhandler.cmd = hmp_info_uuid,
},
-#if defined(TARGET_PPC)
{
.name = "cpustats",
.args_type = "",
.help = "show CPU statistics",
.mhandler.cmd = do_info_cpu_stats,
},
-#endif
#if defined(CONFIG_SLIRP)
{
.name = "usernet",
/* Initialize multiboot mmap structs using int 0x15(e820) */
xor %ebx, %ebx
- /* mmap start after first size */
- movl $4, %edi
+ /* Start storing mmap data at %es:0 */
+ xor %edi, %edi
mmap_loop:
+ /* The multiboot entry size has offset -4, so leave some space */
+ add $4, %di
/* entry size (mmap struct) & max buffer size (int15) */
movl $20, %ecx
- /* store entry size */
- /* old as(1) doesn't like this insn so emit the bytes instead:
- movl %ecx, %es:-4(%edi)
- */
- .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc
/* e820 */
movl $0x0000e820, %eax
/* 'SMAP' magic */
int $0x15
mmap_check_entry:
- /* last entry? then we're done */
+ /* Error or last entry already done? */
jb mmap_done
- and %bx, %bx
- jz mmap_done
- /* valid entry, so let's loop on */
mmap_store_entry:
- /* %ax = entry_number * 24 */
- mov $24, %ax
- mul %bx
- mov %ax, %di
+ /* store entry size */
+ /* old as(1) doesn't like this insn so emit the bytes instead:
+ movl %ecx, %es:-4(%edi)
+ */
+ .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc
+
+ /* %edi += entry_size, store as mbs_mmap_length */
+ add %ecx, %edi
movw %di, %fs:0x2c
- /* %di = 4 + (entry_number * 24) */
- add $4, %di
- jmp mmap_loop
+
+ /* Continuation value 0 means last entry */
+ test %ebx, %ebx
+ jnz mmap_loop
mmap_done:
+ /* Calculate upper_mem field: The amount of memory between 1 MB and
+ the first upper memory hole. Get it from the mmap. */
+ xor %di, %di
+ mov $0x100000, %edx
+upper_mem_entry:
+ cmp %fs:0x2c, %di
+ je upper_mem_done
+ add $4, %di
+
+ /* Skip if type != 1 */
+ cmpl $1, %es:16(%di)
+ jne upper_mem_next
+
+ /* Skip if > 4 GB */
+ movl %es:4(%di), %eax
+ test %eax, %eax
+ jnz upper_mem_next
+
+ /* Check for contiguous extension (base <= %edx < base + length) */
+ movl %es:(%di), %eax
+ cmp %eax, %edx
+ jb upper_mem_next
+ addl %es:8(%di), %eax
+ cmp %eax, %edx
+ jae upper_mem_next
+
+ /* If so, update %edx, and restart the search (mmap isn't ordered) */
+ mov %eax, %edx
+ xor %di, %di
+ jmp upper_mem_entry
+
+upper_mem_next:
+ addl %es:-4(%di), %edi
+ jmp upper_mem_entry
+
+upper_mem_done:
+ sub $0x100000, %edx
+ shr $10, %edx
+ mov %edx, %fs:0x8
+
real_to_prot:
/* Load the GDT before going into protected mode */
lgdt:
# @addr: socket address to listen on (server=true)
# or connect to (server=false)
# @server: #optional create server socket (default: true)
-# @wait: #optional wait for connect (not used for server
-# sockets, default: false)
+# @wait: #optional wait for incoming connection on server
+# sockets (default: false).
# @nodelay: #optional set TCP_NODELAY socket option (default: false)
-# @telnet: #optional enable telnet protocol (default: false)
+# @telnet: #optional enable telnet protocol on server
+# sockets (default: false)
#
# Since: 1.4
##
fd = inet_dgram_opts(opts, &local_err);
if (fd < 0) {
+ qerror_report_err(local_err);
+ error_free(local_err);
return NULL;
}
return qemu_chr_open_udp_fd(fd);
memset(&ss, 0, ss_len);
if (getsockname(fd, (struct sockaddr *) &ss, &ss_len) != 0) {
- error_setg(errp, "getsockname: %s", strerror(errno));
+ error_setg_errno(errp, errno, "getsockname");
return NULL;
}
}
if (is_listen && is_waitconnect) {
- printf("QEMU waiting for connection on: %s\n",
- chr->filename);
+ fprintf(stderr, "QEMU waiting for connection on: %s\n",
+ chr->filename);
tcp_chr_accept(s->listen_chan, G_IO_IN, chr);
qemu_set_nonblock(s->listen_fd);
}
}
}
+static void qemu_chr_parse_mux(QemuOpts *opts, ChardevBackend *backend,
+ Error **errp)
+{
+ const char *chardev = qemu_opt_get(opts, "chardev");
+
+ if (chardev == NULL) {
+ error_setg(errp, "chardev: mux: no chardev given");
+ return;
+ }
+ backend->mux = g_new0(ChardevMux, 1);
+ backend->mux->chardev = g_strdup(chardev);
+}
+
typedef struct CharDriver {
const char *name;
/* old, pre qapi */
CharDriverState *(*open)(QemuOpts *opts);
/* new, qapi-based */
- int kind;
+ ChardevBackendKind kind;
void (*parse)(QemuOpts *opts, ChardevBackend *backend, Error **errp);
} CharDriver;
backends = g_slist_append(backends, s);
}
-void register_char_driver_qapi(const char *name, int kind,
+void register_char_driver_qapi(const char *name, ChardevBackendKind kind,
void (*parse)(QemuOpts *opts, ChardevBackend *backend, Error **errp))
{
CharDriver *s;
if (i == NULL) {
error_setg(errp, "chardev: backend \"%s\" not found",
qemu_opt_get(opts, "backend"));
- return NULL;
+ goto err;
}
if (!cd->open) {
ChardevBackend *backend = g_new0(ChardevBackend, 1);
ChardevReturn *ret = NULL;
const char *id = qemu_opts_id(opts);
- const char *bid = NULL;
+ char *bid = NULL;
if (qemu_opt_get_bool(opts, "mux", 0)) {
bid = g_strdup_printf("%s-base", id);
backend->kind = CHARDEV_BACKEND_KIND_MUX;
backend->mux->chardev = g_strdup(bid);
ret = qmp_chardev_add(id, backend, errp);
- if (error_is_set(errp)) {
- goto qapi_out;
- }
+ assert(!error_is_set(errp));
}
chr = qemu_chr_find(id);
+ chr->opts = opts;
qapi_out:
qapi_free_ChardevBackend(backend);
qapi_free_ChardevReturn(ret);
+ g_free(bid);
return chr;
}
},{
.name = "size",
.type = QEMU_OPT_SIZE,
+ },{
+ .name = "chardev",
+ .type = QEMU_OPT_STRING,
},
{ /* end of list */ }
},
{
HANDLE out;
- if (file->in) {
+ if (file->has_in) {
error_setg(errp, "input file not supported");
return NULL;
}
TFR(fd = qemu_open(src, flags, 0666));
if (fd == -1) {
- error_setg(errp, "open %s: %s", src, strerror(errno));
+ error_setg_file_open(errp, errno, src);
}
return fd;
}
return NULL;
}
- if (file->in) {
+ if (file->has_in) {
flags = O_RDONLY;
in = qmp_chardev_open_file_source(file->in, flags, errp);
if (error_is_set(errp)) {
register_char_driver_qapi("console", CHARDEV_BACKEND_KIND_CONSOLE, NULL);
register_char_driver_qapi("pipe", CHARDEV_BACKEND_KIND_PIPE,
qemu_chr_parse_pipe);
+ register_char_driver_qapi("mux", CHARDEV_BACKEND_KIND_MUX,
+ qemu_chr_parse_mux);
}
type_init(register_types);
SMP is supported with up to 255 CPUs.
-QEMU uses the PC BIOS from the Bochs project and the Plex86/Bochs LGPL
+QEMU uses the PC BIOS from the Seabios project and the Plex86/Bochs LGPL
VGA BIOS.
QEMU uses YM3812 emulation by Tatsuyuki Satoh.
ETEXI
DEF("smp", HAS_ARG, QEMU_OPTION_smp,
- "-smp n[,maxcpus=cpus][,cores=cores][,threads=threads][,sockets=sockets]\n"
+ "-smp [cpus=]n[,maxcpus=cpus][,cores=cores][,threads=threads][,sockets=sockets]\n"
" set the number of CPUs to 'n' [default=1]\n"
" maxcpus= maximum number of total cpus, including\n"
" offline CPUs for hotplug, etc\n"
" sockets= number of discrete sockets in the system\n",
QEMU_ARCH_ALL)
STEXI
-@item -smp @var{n}[,cores=@var{cores}][,threads=@var{threads}][,sockets=@var{sockets}][,maxcpus=@var{maxcpus}]
+@item -smp [cpus=]@var{n}[,cores=@var{cores}][,threads=@var{threads}][,sockets=@var{sockets}][,maxcpus=@var{maxcpus}]
@findex -smp
Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255
CPUs are supported. On Sparc32 target, Linux limits the number of usable CPUs
* <http://www.gnu.org/licenses/gpl-2.0.html>
*/
-#include "qom/cpu.h"
#include "qemu-common.h"
+#include "qom/cpu.h"
#include "sysemu/kvm.h"
#include "qemu/notify.h"
#include "sysemu/sysemu.h"
cpu->interrupt_request &= ~mask;
}
+void cpu_exit(CPUState *cpu)
+{
+ cpu->exit_request = 1;
+ cpu->tcg_exit_req = 1;
+}
+
int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
}
+void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->dump_state) {
+ cc->dump_state(cpu, f, cpu_fprintf, flags);
+ }
+}
+
+void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->dump_statistics) {
+ cc->dump_statistics(cpu, f, cpu_fprintf, flags);
+ }
+}
+
void cpu_reset(CPUState *cpu)
{
CPUClass *klass = CPU_GET_CLASS(cpu);
{
CPUState *cpu = CPU(dev);
+ qemu_init_vcpu(cpu);
+
if (dev->hotplugged) {
cpu_synchronize_post_init(cpu);
notifier_list_notify(&cpu_added_notifiers, dev);
+#include "qemu-common.h"
#include "qom/cpu.h"
void cpu_resume(CPUState *cpu)
{
}
+
+void qemu_init_vcpu(CPUState *cpu)
+{
+}
#define ENV_OFFSET offsetof(AlphaCPU, env)
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_alpha_cpu;
+#endif
+
void alpha_cpu_do_interrupt(CPUState *cpu);
+void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
- AlphaCPU *cpu = ALPHA_CPU(dev);
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
-
acc->parent_realize(dev, errp);
}
cc->class_by_name = alpha_cpu_class_by_name;
cc->do_interrupt = alpha_cpu_do_interrupt;
+ cc->dump_state = alpha_cpu_dump_state;
+ cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access);
+ device_class_set_vmsd(dc, &vmstate_alpha_cpu);
}
static const TypeInfo alpha_cpu_type_info = {
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUAlphaState *env);
-QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
- hwaddr addr, int is_write,
- int is_exec, int unused, int size);
+QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec,
+ int unused, unsigned size);
#endif
/* Bits in TB->FLAGS that control how translation is processed. */
#endif /* !USER_ONLY */
}
-void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
static const char *linux_reg_names[] = {
"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
};
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
int i;
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
.put = put_fpcr,
};
-static VMStateField vmstate_cpu_fields[] = {
+static VMStateField vmstate_env_fields[] = {
VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
/* Save the architecture value of the fpcr, not the internally
VMSTATE_END_OF_LIST()
};
-static const VMStateDescription vmstate_cpu = {
- .name = "cpu",
+static const VMStateDescription vmstate_env = {
+ .name = "env",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = vmstate_cpu_fields,
+ .fields = vmstate_env_fields,
};
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
+static VMStateField vmstate_cpu_fields[] = {
+ VMSTATE_CPU(),
+ VMSTATE_STRUCT(env, AlphaCPU, 1, vmstate_env, CPUAlphaState),
+ VMSTATE_END_OF_LIST()
+};
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
+const VMStateDescription vmstate_alpha_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = vmstate_cpu_fields,
+};
cpu_loop_exit(env);
}
-void cpu_unassigned_access(CPUAlphaState *env, hwaddr addr,
- int is_write, int is_exec, int unused, int size)
+void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
+ bool is_write, bool is_exec, int unused,
+ unsigned size)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
+
env->trap_arg0 = addr;
- env->trap_arg1 = is_write;
+ env->trap_arg1 = is_write ? 1 : 0;
dynamic_excp(env, 0, EXCP_MCHK, 0);
}
#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
uint32_t do_arm_semihosting(CPUARMState *env)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
char * s;
exit(0);
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
abort();
}
}
void arm_cpu_do_interrupt(CPUState *cpu);
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
+void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
#endif
init_cpreg_list(cpu);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(env);
acc->parent_realize(dev, errp);
}
cc->class_by_name = arm_cpu_class_by_name;
cc->do_interrupt = arm_cpu_do_interrupt;
+ cc->dump_state = arm_cpu_dump_state;
cpu_class_set_vmsd(cc, &vmstate_arm_cpu);
}
"???", "???", "???", "und", "???", "???", "???", "sys"
};
-void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
int i;
uint32_t psr;
void cris_cpu_do_interrupt(CPUState *cpu);
void crisv10_cpu_do_interrupt(CPUState *cpu);
+void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
#endif
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
ccc->parent_realize(dev, errp);
}
cc->class_by_name = cris_cpu_class_by_name;
cc->do_interrupt = cris_cpu_do_interrupt;
+ cc->dump_state = cris_cpu_dump_state;
}
static const TypeInfo cris_cpu_type_info = {
int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx)
{
+ CRISCPU *cpu = cris_env_get_cpu(env);
+
env->exception_index = 0xaa;
env->pregs[PR_EDA] = address;
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
return 1;
}
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int i;
uint32_t srs;
void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
#endif
#endif
mce_init(cpu);
- qemu_init_vcpu(&cpu->env);
x86_cpu_apic_realize(cpu, &local_err);
if (local_err != NULL) {
cc->reset = x86_cpu_reset;
cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->dump_state = x86_cpu_dump_state;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
#define DUMP_CODE_BYTES_TOTAL 50
#define DUMP_CODE_BYTES_BACKWARD 20
-void cpu_dump_state(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int eflags, i, nb;
char cc_op_name[32];
static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cs);
eflags = cpu_compute_eflags(env);
#ifdef TARGET_X86_64
CPUState *cpu = CPU(params->cpu);
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
- cpu_synchronize_state(cenv);
+ cpu_synchronize_state(cpu);
/*
* If there is an MCE exception being processed, ignore this SRAO MCE
cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
if (env->exception_injected == EXCP08_DBLE) {
/* this means triple fault */
cs->halted = 0;
}
if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
do_cpu_init(cpu);
}
if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
do_cpu_sipi(cpu);
}
if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
apic_handle_tpr_access_report(env->apic_state, env->eip,
env->tpr_access_type);
}
ret = EXCP_DEBUG;
}
if (ret == 0) {
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(cpu));
assert(env->exception_injected == -1);
/* pass to guest */
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- kvm_cpu_synchronize_state(env);
+ kvm_cpu_synchronize_state(cs);
return !(env->cr[0] & CR0_PE_MASK) ||
((env->segs[R_CS].selector & 3) != 3);
}
#endif
void lm32_cpu_do_interrupt(CPUState *cpu);
+void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
-
lcc->parent_realize(dev, errp);
}
cc->reset = lm32_cpu_reset;
cc->do_interrupt = lm32_cpu_do_interrupt;
+ cc->dump_state = lm32_cpu_dump_state;
cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
}
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
int i;
if (!env || !f) {
#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
+void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
m68k_cpu_init_gdb(cpu);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
mcc->parent_realize(dev, errp);
}
cc->class_by_name = m68k_cpu_class_by_name;
cc->do_interrupt = m68k_cpu_do_interrupt;
+ cc->dump_state = m68k_cpu_dump_state;
dc->vmsd = &vmstate_m68k_cpu;
}
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUM68KState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
int i;
uint16_t sr;
CPU_DoubleU u;
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
+void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
mcc->parent_realize(dev, errp);
}
cc->reset = mb_cpu_reset;
cc->do_interrupt = mb_cpu_do_interrupt;
+ cc->dump_state = mb_cpu_dump_state;
+ cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access);
dc->vmsd = &vmstate_mb_cpu;
-
dc->props = mb_properties;
}
}
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUMBState *env1, hwaddr addr,
- int is_write, int is_exec, int is_asi, int size);
+void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec, int is_asi,
+ unsigned size);
#endif
static inline bool cpu_has_work(CPUState *cpu)
int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
int mmu_idx)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+
env->exception_index = 0xaa;
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
return 1;
}
mmu_write(env, rn, v);
}
-void cpu_unassigned_access(CPUMBState *env, hwaddr addr,
- int is_write, int is_exec, int is_asi, int size)
+void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
+ bool is_write, bool is_exec, int is_asi,
+ unsigned size)
{
+ MicroBlazeCPU *cpu;
+ CPUMBState *env;
+
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
- addr, is_write, is_exec);
- if (!env || !(env->sregs[SR_MSR] & MSR_EE)) {
+ addr, is_write ? 1 : 0, is_exec ? 1 : 0);
+ if (cs == NULL) {
+ return;
+ }
+ cpu = MICROBLAZE_CPU(cs);
+ env = &cpu->env;
+ if (!(env->sregs[SR_MSR] & MSR_EE)) {
return;
}
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
int i;
if (!env || !f)
#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_do_interrupt(CPUState *cpu);
+void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
mcc->parent_realize(dev, errp);
}
cc->reset = mips_cpu_reset;
cc->do_interrupt = mips_cpu_do_interrupt;
+ cc->dump_state = mips_cpu_dump_state;
+ cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access);
}
static const TypeInfo mips_cpu_type_info = {
void r4k_helper_tlbp(CPUMIPSState *env);
void r4k_helper_tlbr(CPUMIPSState *env);
-void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
- int is_write, int is_exec, int unused, int size);
+void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec, int unused,
+ unsigned size);
#endif
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
}
}
-void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
- int is_write, int is_exec, int unused, int size)
+void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
+ bool is_write, bool is_exec, int unused,
+ unsigned size)
{
- if (is_exec)
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ if (is_exec) {
helper_raise_exception(env, EXCP_IBE);
- else
+ } else {
helper_raise_exception(env, EXCP_DBE);
+ }
}
#endif /* !CONFIG_USER_ONLY */
}
#endif
-void cpu_dump_state (CPUMIPSState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
int i;
cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
{
MoxieCPU *cpu = MOXIE_CPU(dev);
- MoxieCPUClass *occ = MOXIE_CPU_GET_CLASS(dev);
+ MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu));
- occ->parent_realize(dev, errp);
+ mcc->parent_realize(dev, errp);
}
static void moxie_cpu_initfn(Object *obj)
cc->class_by_name = moxie_cpu_class_by_name;
- cpu_class_set_vmsd(cc, &vmstate_moxie_cpu);
cc->do_interrupt = moxie_cpu_do_interrupt;
+ cc->dump_state = moxie_cpu_dump_state;
+ cpu_class_set_vmsd(cc, &vmstate_moxie_cpu);
}
static void moxielite_initfn(Object *obj)
MoxieCPU *cpu_moxie_init(const char *cpu_model);
int cpu_moxie_exec(CPUMoxieState *s);
void moxie_cpu_do_interrupt(CPUState *cs);
+void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
void moxie_translate_init(void);
int cpu_moxie_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
int rw, int mmu_idx)
{
+ MoxieCPU *cpu = moxie_env_get_cpu(env);
+
env->exception_index = 0xaa;
env->debug1 = address;
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
return 1;
}
return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
}
-void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ MoxieCPU *cpu = MOXIE_CPU(cs);
+ CPUMoxieState *env = &cpu->env;
int i;
cpu_fprintf(f, "pc=0x%08x\n", env->pc);
cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
OpenRISCCPU *cpu = OPENRISC_CPU(dev);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu));
occ->parent_realize(dev, errp);
cc->class_by_name = openrisc_cpu_class_by_name;
cc->do_interrupt = openrisc_cpu_do_interrupt;
+ cc->dump_state = openrisc_cpu_dump_state;
+ device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
}
static void cpu_register(const OpenRISCCPUInfo *info)
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s);
void openrisc_cpu_do_interrupt(CPUState *cpu);
+void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
void openrisc_translate_init(void);
int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
target_ulong address,
#define cpu_signal_handler cpu_openrisc_signal_handler
#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_openrisc_cpu;
+
/* hw/openrisc_pic.c */
void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
#include "hw/hw.h"
#include "hw/boards.h"
-static const VMStateDescription vmstate_cpu = {
- .name = "cpu",
+static const VMStateDescription vmstate_env = {
+ .name = "env",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
VMSTATE_UINT32(sr, CPUOpenRISCState),
}
};
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
+const VMStateDescription vmstate_openrisc_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CPU(),
+ VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
}
-void cpu_dump_state(CPUOpenRISCState *env, FILE *f,
- fprintf_function cpu_fprintf,
- int flags)
+void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf,
+ int flags)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ CPUOpenRISCState *env = &cpu->env;
int i;
- uint32_t *regs = env->gpr;
+
cpu_fprintf(f, "PC=%08x\n", env->pc);
for (i = 0; i < 32; ++i) {
- cpu_fprintf(f, "R%02d=%08x%c", i, regs[i],
+ cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
(i % 4) == 3 ? '\n' : ' ');
}
}
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
void ppc_cpu_do_interrupt(CPUState *cpu);
+void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#endif
int i;
uint64_t slbe, slbv;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
for (i = 0; i < env->slb_nr; i++) {
/*****************************************************************************/
/* Misc PowerPC helpers */
-void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
#define RGPL 4
#define RFPL 4
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
int i;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cs);
cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
#undef RFPL
}
-void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
- int flags)
+void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
+ fprintf_function cpu_fprintf, int flags)
{
#if defined(DO_PPC_STATISTICS)
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
opc_handler_t **t1, **t2, **t3, *handler;
int op1, op2, op3;
- t1 = env->opcodes;
+ t1 = cpu->env.opcodes;
for (op1 = 0; op1 < 64; op1++) {
handler = t1[op1];
if (is_indirect_opcode(handler)) {
34, "power-spe.xml", 0);
}
- qemu_init_vcpu(env);
-
pcc->parent_realize(dev, errp);
#if defined(PPC_DUMP_CPU)
cc->class_by_name = ppc_cpu_class_by_name;
cc->do_interrupt = ppc_cpu_do_interrupt;
+ cc->dump_state = ppc_cpu_dump_state;
+ cc->dump_statistics = ppc_cpu_dump_statistics;
}
static const TypeInfo ppc_cpu_type_info = {
#define ENV_OFFSET offsetof(S390CPU, env)
void s390_cpu_do_interrupt(CPUState *cpu);
+void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
#endif
S390CPU *cpu = S390_CPU(dev);
S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu));
scc->parent_realize(dev, errp);
cc->reset = s390_cpu_reset;
cc->do_interrupt = s390_cpu_do_interrupt;
+ cc->dump_state = s390_cpu_dump_state;
dc->vmsd = &vmstate_s390_cpu;
}
uint64_t code;
int r = 0;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(cpu));
sccb = env->regs[ipbh0 & 0xf];
code = env->regs[(ipbh0 & 0xf0) >> 4];
static int s390_cpu_initial_reset(S390CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
int i;
s390_del_running_cpu(cpu);
- if (kvm_vcpu_ioctl(CPU(cpu), KVM_S390_INITIAL_RESET, NULL) < 0) {
+ if (kvm_vcpu_ioctl(cs, KVM_S390_INITIAL_RESET, NULL) < 0) {
perror("cannot init reset vcpu");
}
/* Manually zero out all registers */
- cpu_synchronize_state(env);
+ cpu_synchronize_state(cs);
for (i = 0; i < 16; i++) {
env->regs[i] = 0;
}
S390CPU *target_cpu;
CPUS390XState *target_env;
- cpu_synchronize_state(env);
+ cpu_synchronize_state(CPU(cpu));
/* get order code */
order_code = run->s390_sieic.ipb >> 28;
return pc;
}
-void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
int i;
if (env->cc_op > 3) {
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
+void superh_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#endif
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
scc->parent_realize(dev, errp);
}
cc->class_by_name = superh_cpu_class_by_name;
cc->do_interrupt = superh_cpu_do_interrupt;
+ cc->dump_state = superh_cpu_dump_state;
dc->vmsd = &vmstate_sh_cpu;
}
done_init = 1;
}
-void cpu_dump_state(CPUSH4State * env, FILE * f,
- int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
- int flags)
+void superh_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
int i;
cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
env->pc, env->sr, env->pr, env->fpscr);
#define ENV_OFFSET offsetof(SPARCCPU, env)
void sparc_cpu_do_interrupt(CPUState *cpu);
+void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#endif
#define REGS_PER_LINE 8
#endif
-void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
int i, x;
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
- SPARCCPU *cpu = SPARC_CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
-
scc->parent_realize(dev, errp);
}
cc->reset = sparc_cpu_reset;
cc->do_interrupt = sparc_cpu_do_interrupt;
+ cc->dump_state = sparc_cpu_dump_state;
+ cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access);
}
static const TypeInfo sparc_cpu_type_info = {
/* cpu-exec.c */
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUSPARCState *env1, hwaddr addr,
- int is_write, int is_exec, int is_asi, int size);
+void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec, int is_asi,
+ unsigned size);
#if defined(TARGET_SPARC64)
hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx);
break;
case 8: /* User code access, XXX */
default:
- cpu_unassigned_access(env, addr, 0, 0, asi, size);
+ cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
+ addr, false, false, asi, size);
ret = 0;
break;
}
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
- cpu_unassigned_access(env, addr, 1, 0, asi, size);
+ cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
+ addr, true, false, asi, size);
break;
}
#ifdef DEBUG_ASI
case 0x5f: /* D-MMU demap, WO */
case 0x77: /* Interrupt vector, WO */
default:
- cpu_unassigned_access(env, addr, 0, 0, 1, size);
+ cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
+ addr, false, false, 1, size);
ret = 0;
break;
}
case 0x8a: /* Primary no-fault LE, RO */
case 0x8b: /* Secondary no-fault LE, RO */
default:
- cpu_unassigned_access(env, addr, 1, 0, 1, size);
+ cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
+ addr, true, false, 1, size);
return;
}
}
#if !defined(CONFIG_USER_ONLY)
#ifndef TARGET_SPARC64
-void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
- int is_write, int is_exec, int is_asi, int size)
+void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
+ bool is_write, bool is_exec, int is_asi,
+ unsigned size)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
int fault_type;
#ifdef DEBUG_UNASSIGNED
}
}
#else
-void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
- int is_write, int is_exec, int is_asi, int size)
+void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
+ bool is_write, bool is_exec, int is_asi,
+ unsigned size)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
"\n", addr, env->pc);
#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
+void uc32_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#endif
static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
{
- UniCore32CPU *cpu = UNICORE32_CPU(dev);
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
-
ucc->parent_realize(dev, errp);
}
cc->class_by_name = uc32_cpu_class_by_name;
cc->do_interrupt = uc32_cpu_do_interrupt;
+ cc->dump_state = uc32_cpu_dump_state;
dc->vmsd = &vmstate_uc32_cpu;
}
#define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
#endif
-void cpu_dump_state(CPUUniCore32State *env, FILE *f,
- fprintf_function cpu_fprintf, int flags)
+void uc32_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
int i;
uint32_t psr;
#define ENV_OFFSET offsetof(XtensaCPU, env)
void xtensa_cpu_do_interrupt(CPUState *cpu);
+void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#endif
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
- XtensaCPU *cpu = XTENSA_CPU(dev);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
- qemu_init_vcpu(&cpu->env);
-
xcc->parent_realize(dev, errp);
}
cc->reset = xtensa_cpu_reset;
cc->do_interrupt = xtensa_cpu_do_interrupt;
+ cc->dump_state = xtensa_cpu_dump_state;
dc->vmsd = &vmstate_xtensa_cpu;
}
void HELPER(dump_state)(CPUXtensaState *env)
{
- cpu_dump_state(env, stderr, fprintf, 0);
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
}
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
int i, j;
cpu_fprintf(f, "PC=%08x\n\n", env->pc);
*/
DisplayState *init_displaystate(void)
{
+ Error *local_err = NULL;
+ gchar *name;
int i;
if (!display_state) {
consoles[i]->ds == NULL) {
text_console_do_init(consoles[i]->chr, display_state);
}
+
+ /* Hook up into the qom tree here (not in new_console()), once
+ * all QemuConsoles are created and the order / numbering
+ * doesn't change any more */
+ name = g_strdup_printf("console[%d]", i);
+ object_property_add_child(container_get(object_get_root(), "/backend"),
+ name, OBJECT(consoles[i]), &local_err);
+ g_free(name);
}
return display_state;
GtkWidget *notebook;
GtkWidget *drawing_area;
cairo_surface_t *surface;
+ pixman_image_t *convert;
DisplayChangeListener dcl;
DisplaySurface *ds;
int button_mask;
DPRINTF("update(x=%d, y=%d, w=%d, h=%d)\n", x, y, w, h);
+ if (s->convert) {
+ pixman_image_composite(PIXMAN_OP_SRC, s->ds->image, NULL, s->convert,
+ x, y, 0, 0, x, y, w, h);
+ }
+
x1 = floor(x * s->scale_x);
y1 = floor(y * s->scale_y);
DisplaySurface *surface)
{
GtkDisplayState *s = container_of(dcl, GtkDisplayState, dcl);
- cairo_format_t kind;
bool resized = true;
- int stride;
DPRINTF("resize(width=%d, height=%d)\n",
surface_width(surface), surface_height(surface));
resized = false;
}
s->ds = surface;
- switch (surface_bits_per_pixel(surface)) {
- case 8:
- kind = CAIRO_FORMAT_A8;
- break;
- case 16:
- kind = CAIRO_FORMAT_RGB16_565;
- break;
- case 32:
- kind = CAIRO_FORMAT_RGB24;
- break;
- default:
- g_assert_not_reached();
- break;
- }
- stride = cairo_format_stride_for_width(kind, surface_width(surface));
- g_assert(surface_stride(surface) == stride);
+ if (s->convert) {
+ pixman_image_unref(s->convert);
+ s->convert = NULL;
+ }
- s->surface = cairo_image_surface_create_for_data(surface_data(surface),
- kind,
- surface_width(surface),
- surface_height(surface),
- surface_stride(surface));
+ if (surface->format == PIXMAN_x8r8g8b8) {
+ /*
+ * PIXMAN_x8r8g8b8 == CAIRO_FORMAT_RGB24
+ *
+ * No need to convert, use surface directly. Should be the
+ * common case as this is qemu_default_pixelformat(32) too.
+ */
+ s->surface = cairo_image_surface_create_for_data
+ (surface_data(surface),
+ CAIRO_FORMAT_RGB24,
+ surface_width(surface),
+ surface_height(surface),
+ surface_stride(surface));
+ } else {
+ /* Must convert surface, use pixman to do it. */
+ s->convert = pixman_image_create_bits(PIXMAN_x8r8g8b8,
+ surface_width(surface),
+ surface_height(surface),
+ NULL, 0);
+ s->surface = cairo_image_surface_create_for_data
+ ((void *)pixman_image_get_data(s->convert),
+ CAIRO_FORMAT_RGB24,
+ pixman_image_get_width(s->convert),
+ pixman_image_get_height(s->convert),
+ pixman_image_get_stride(s->convert));
+ pixman_image_composite(PIXMAN_OP_SRC, s->ds->image, NULL, s->convert,
+ 0, 0, 0, 0, 0, 0,
+ pixman_image_get_width(s->convert),
+ pixman_image_get_height(s->convert));
+ }
if (resized) {
gd_update_windowsize(s);
SocketAddress *socket_parse(const char *str, Error **errp)
{
- SocketAddress *addr = NULL;
+ SocketAddress *addr;
- addr = g_new(SocketAddress, 1);
+ addr = g_new0(SocketAddress, 1);
if (strstart(str, "unix:", NULL)) {
if (str[5] == '\0') {
error_setg(errp, "invalid Unix socket address");
}
} else {
addr->kind = SOCKET_ADDRESS_KIND_INET;
- addr->inet = g_new(InetSocketAddress, 1);
addr->inet = inet_parse(str, errp);
if (addr->inet == NULL) {
goto fail;
case SOCKET_ADDRESS_KIND_FD:
fd = monitor_get_fd(cur_mon, addr->fd->str, errp);
- if (callback) {
+ if (fd >= 0 && callback) {
qemu_set_nonblock(fd);
callback(fd, opaque);
}
default:
error_setg(errp, "socket type unsupported for datagram");
- return -1;
+ fd = -1;
}
qemu_opts_del(opts);
return fd;
}
}
-static void smp_parse(const char *optarg)
+static QemuOptsList qemu_smp_opts = {
+ .name = "smp-opts",
+ .implied_opt_name = "cpus",
+ .merge_lists = true,
+ .head = QTAILQ_HEAD_INITIALIZER(qemu_smp_opts.head),
+ .desc = {
+ {
+ .name = "cpus",
+ .type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "sockets",
+ .type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "cores",
+ .type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "threads",
+ .type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "maxcpus",
+ .type = QEMU_OPT_NUMBER,
+ },
+ { /*End of list */ }
+ },
+};
+
+static void smp_parse(QemuOpts *opts)
{
- int smp, sockets = 0, threads = 0, cores = 0;
- char *endptr;
- char option[128];
+ if (opts) {
- smp = strtoul(optarg, &endptr, 10);
- if (endptr != optarg) {
- if (*endptr == ',') {
- endptr++;
- }
- }
- if (get_param_value(option, 128, "sockets", endptr) != 0)
- sockets = strtoull(option, NULL, 10);
- if (get_param_value(option, 128, "cores", endptr) != 0)
- cores = strtoull(option, NULL, 10);
- if (get_param_value(option, 128, "threads", endptr) != 0)
- threads = strtoull(option, NULL, 10);
- if (get_param_value(option, 128, "maxcpus", endptr) != 0)
- max_cpus = strtoull(option, NULL, 10);
-
- /* compute missing values, prefer sockets over cores over threads */
- if (smp == 0 || sockets == 0) {
- sockets = sockets > 0 ? sockets : 1;
- cores = cores > 0 ? cores : 1;
- threads = threads > 0 ? threads : 1;
- if (smp == 0) {
- smp = cores * threads * sockets;
- }
- } else {
- if (cores == 0) {
+ unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
+ unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
+ unsigned cores = qemu_opt_get_number(opts, "cores", 0);
+ unsigned threads = qemu_opt_get_number(opts, "threads", 0);
+
+ /* compute missing values, prefer sockets over cores over threads */
+ if (cpus == 0 || sockets == 0) {
+ sockets = sockets > 0 ? sockets : 1;
+ cores = cores > 0 ? cores : 1;
threads = threads > 0 ? threads : 1;
- cores = smp / (sockets * threads);
+ if (cpus == 0) {
+ cpus = cores * threads * sockets;
+ }
} else {
- threads = smp / (cores * sockets);
+ if (cores == 0) {
+ threads = threads > 0 ? threads : 1;
+ cores = cpus / (sockets * threads);
+ } else {
+ threads = cpus / (cores * sockets);
+ }
}
+
+ max_cpus = qemu_opt_get_number(opts, "maxcpus", 0);
+
+ smp_cpus = cpus;
+ smp_cores = cores > 0 ? cores : 1;
+ smp_threads = threads > 0 ? threads : 1;
+
}
- smp_cpus = smp;
- smp_cores = cores > 0 ? cores : 1;
- smp_threads = threads > 0 ? threads : 1;
- if (max_cpus == 0)
+
+ if (max_cpus == 0) {
max_cpus = smp_cpus;
+ }
+
+ if (max_cpus > 255) {
+ fprintf(stderr, "Unsupported number of maxcpus\n");
+ exit(1);
+ }
+ if (max_cpus < smp_cpus) {
+ fprintf(stderr, "maxcpus must be equal to or greater than smp\n");
+ exit(1);
+ }
+
}
static void configure_realtime(QemuOpts *opts)
qemu_add_opts(&qemu_trace_opts);
qemu_add_opts(&qemu_option_rom_opts);
qemu_add_opts(&qemu_machine_opts);
+ qemu_add_opts(&qemu_smp_opts);
qemu_add_opts(&qemu_boot_opts);
qemu_add_opts(&qemu_sandbox_opts);
qemu_add_opts(&qemu_add_fd_opts);
}
break;
case QEMU_OPTION_smp:
- smp_parse(optarg);
- if (smp_cpus < 1) {
- fprintf(stderr, "Invalid number of CPUs\n");
- exit(1);
- }
- if (max_cpus < smp_cpus) {
- fprintf(stderr, "maxcpus must be equal to or greater than "
- "smp\n");
- exit(1);
- }
- if (max_cpus > 255) {
- fprintf(stderr, "Unsupported number of maxcpus\n");
+ if (!qemu_opts_parse(qemu_find_opts("smp-opts"), optarg, 1)) {
exit(1);
}
break;
data_dir[data_dir_idx++] = CONFIG_QEMU_DATADIR;
}
- /*
- * Default to max_cpus = smp_cpus, in case the user doesn't
- * specify a max_cpus value.
- */
- if (!max_cpus)
- max_cpus = smp_cpus;
+ smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
machine->max_cpus = machine->max_cpus ?: 1; /* Default to UP */
if (smp_cpus > machine->max_cpus) {
projects / mirror_qemu.git / commitdiff