clk: sunxi: add gating support to PLL1

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 91a748fed13d0c540084781ee8cd68491d4f5bfd..b8c6cc449a3e42caa7eb1714f8a1f4e67605d575 100644 (file)
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
 Required properties:
 - compatible : shall be one of the following:
        "allwinner,sun4i-osc-clk" - for a gatable oscillator
-       "allwinner,sun4i-pll1-clk" - for the main PLL clock
+       "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
        "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
        "allwinner,sun4i-axi-clk" - for the AXI clock

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index bae5e32c51bdee8ec8b4d18e4b3f8e810b636c3b..eeb623bec5ff2de6fc13dcaeffc1566e598324e7 100644 (file)
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_apb1_config = {
 };
 
 static const struct factors_data sun4i_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun4i_pll1_config,
        .getter = sun4i_get_pll1_factors,
 };
 
 static const struct factors_data sun6i_a31_pll1_data __initconst = {
+       .enable = 31,
        .table = &sun6i_a31_pll1_config,
        .getter = sun6i_a31_get_pll1_factors,
 };