goto err;
}
+ if (ncs[i]) {
+ ret = -EINVAL;
+ goto err;
+ }
+
ncs[i] = peers[i];
ncs[i]->queue_index = i;
}
*ptr = NULL;
return;
}
+ if (*ptr) {
+ error_set_from_qdev_prop_error(errp, -EINVAL, dev, prop, name);
+ return;
+ }
hubport = net_hub_port_find(id);
if (!hubport) {
static void build_append_nameseg(GArray *array, const char *format, ...)
{
- GString *s = g_string_new("");
+ /* It would be nicer to use g_string_vprintf but it's only there in 2.22 */
+ char s[] = "XXXX";
+ int len;
va_list args;
va_start(args, format);
- g_string_vprintf(s, format, args);
+ len = vsnprintf(s, sizeof s, format, args);
va_end(args);
- assert(s->len == 4);
- g_array_append_vals(array, s->str, s->len);
- g_string_free(s, true);
+ assert(len == 4);
+ g_array_append_vals(array, s, len);
}
/* 5.4 Definition Block Encoding */
static unsigned acpi_data_len(GArray *table)
{
- return table->len * g_array_get_element_size(table);
+#if GLIB_CHECK_VERSION(2, 14, 0)
+ assert(g_array_get_element_size(table) == 1);
+#endif
+ return table->len;
}
static void acpi_align_size(GArray *blob, unsigned align)
GArray *bios_linker_loader_init(void)
{
- return g_array_new(false, true /* clear */, sizeof(BiosLinkerLoaderEntry));
+ return g_array_new(false, true /* clear */, 1);
}
/* Free linker wrapper and return the linker array. */
BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH);
/* Alloc entries must come first, so prepend them */
- g_array_prepend_val(linker, entry);
+ g_array_prepend_vals(linker, &entry, sizeof entry);
}
void bios_linker_loader_add_checksum(GArray *linker, const char *file,
entry.cksum.start = cpu_to_le32((uint8_t *)start - (uint8_t *)table);
entry.cksum.length = cpu_to_le32(size);
- g_array_append_val(linker, entry);
+ g_array_append_vals(linker, &entry, sizeof entry);
}
void bios_linker_loader_add_pointer(GArray *linker,
assert(pointer_size == 1 || pointer_size == 2 ||
pointer_size == 4 || pointer_size == 8);
- g_array_append_val(linker, entry);
+ g_array_append_vals(linker, &entry, sizeof entry);
}
uint64_t val = 0;
int fd = dev_region->region->resource_fd;
- if (fd >= 0) {
- if (data) {
- DEBUG("pwrite data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
- ", addr="TARGET_FMT_plx"\n", *data, size, addr, addr);
- if (pwrite(fd, data, size, addr) != size) {
- error_report("%s - pwrite failed %s",
- __func__, strerror(errno));
- }
- } else {
- if (pread(fd, &val, size, addr) != size) {
- error_report("%s - pread failed %s",
- __func__, strerror(errno));
- val = (1UL << (size * 8)) - 1;
- }
- DEBUG("pread val=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
- ", addr=" TARGET_FMT_plx "\n", val, size, addr, addr);
+ if (data) {
+ DEBUG("pwrite data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
+ ", addr="TARGET_FMT_plx"\n", *data, size, addr, addr);
+ if (pwrite(fd, data, size, addr) != size) {
+ error_report("%s - pwrite failed %s", __func__, strerror(errno));
}
} else {
- uint32_t port = addr + dev_region->u.r_baseport;
-
- if (data) {
- DEBUG("out data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
- ", host=%x\n", *data, size, addr, port);
- switch (size) {
- case 1:
- outb(*data, port);
- break;
- case 2:
- outw(*data, port);
- break;
- case 4:
- outl(*data, port);
- break;
- }
- } else {
- switch (size) {
- case 1:
- val = inb(port);
- break;
- case 2:
- val = inw(port);
- break;
- case 4:
- val = inl(port);
- break;
- }
- DEBUG("in data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
- ", host=%x\n", val, size, addr, port);
+ if (pread(fd, &val, size, addr) != size) {
+ error_report("%s - pread failed %s", __func__, strerror(errno));
+ val = (1UL << (size * 8)) - 1;
}
+ DEBUG("pread val=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
+ ", addr=" TARGET_FMT_plx "\n", val, size, addr, addr);
}
return val;
}
void cpu_openrisc_count_update(OpenRISCCPU *cpu)
{
- uint64_t now, next;
- uint32_t wait;
+ uint64_t now;
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (!is_counting) {
- timer_del(cpu->env.timer);
- last_clk = now;
return;
}
-
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
cpu->env.ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ,
get_ticks_per_sec());
last_clk = now;
+}
+
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
+{
+ uint32_t wait;
+ uint64_t now, next;
+
+ if (!is_counting) {
+ return;
+ }
+
+ cpu_openrisc_count_update(cpu);
+ now = last_clk;
if ((cpu->env.ttmr & TTMR_TP) <= (cpu->env.ttcr & TTMR_TP)) {
wait = TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1;
} else {
wait = (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP);
}
-
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
timer_mod(cpu->env.timer, next);
}
void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
{
- is_counting = 0;
+ timer_del(cpu->env.timer);
cpu_openrisc_count_update(cpu);
+ is_counting = 0;
}
static void openrisc_timer_cb(void *opaque)
break;
case TIMER_INTR:
cpu->env.ttcr = 0;
- cpu_openrisc_count_start(cpu);
break;
case TIMER_SHOT:
cpu_openrisc_count_stop(cpu);
break;
case TIMER_CONT:
- cpu_openrisc_count_start(cpu);
break;
}
+
+ cpu_openrisc_timer_update(cpu);
}
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
static int s390_ipl_init(SysBusDevice *dev)
{
S390IPLState *ipl = S390_IPL(dev);
- ram_addr_t kernel_size = 0;
+ int kernel_size;
if (!ipl->kernel) {
- ram_addr_t bios_size = 0;
+ int bios_size;
char *bios_filename;
/* Load zipl bootloader */
bios_size = load_elf(bios_filename, NULL, NULL, &ipl->start_addr, NULL,
NULL, 1, ELF_MACHINE, 0);
- if (bios_size == -1UL) {
+ if (bios_size == -1) {
bios_size = load_image_targphys(bios_filename, ZIPL_IMAGE_START,
4096);
ipl->start_addr = ZIPL_IMAGE_START;
}
g_free(bios_filename);
- if ((long)bios_size < 0) {
+ if (bios_size == -1) {
hw_error("could not load bootloader '%s'\n", bios_name);
}
return 0;
} else {
kernel_size = load_elf(ipl->kernel, NULL, NULL, NULL, NULL,
NULL, 1, ELF_MACHINE, 0);
- if (kernel_size == -1UL) {
+ if (kernel_size == -1) {
kernel_size = load_image_targphys(ipl->kernel, 0, ram_size);
}
- if (kernel_size == -1UL) {
+ if (kernel_size == -1) {
fprintf(stderr, "could not load kernel '%s'\n", ipl->kernel);
return -1;
}
ipl->start_addr = KERN_IMAGE_START;
}
if (ipl->initrd) {
- ram_addr_t initrd_offset, initrd_size;
+ ram_addr_t initrd_offset;
+ int initrd_size;
initrd_offset = INITRD_START;
while (kernel_size + 0x100000 > initrd_offset) {
}
initrd_size = load_image_targphys(ipl->initrd, initrd_offset,
ram_size - initrd_offset);
- if (initrd_size == -1UL) {
+ if (initrd_size == -1) {
fprintf(stderr, "qemu: could not load initrd '%s'\n", ipl->initrd);
exit(1);
}
VirtIORNG *vrng = VIRTIO_RNG(vdev);
Error *local_err = NULL;
+ if (!vrng->conf.period_ms > 0) {
+ qerror_report(QERR_INVALID_PARAMETER_VALUE, "period",
+ "a positive number");
+ return -1;
+ }
+
if (vrng->conf.rng == NULL) {
vrng->conf.default_backend = RNG_RANDOM(object_new(TYPE_RNG_RANDOM));
const GUID CLSID_COMAdminCatalog = { 0xF618C514, 0xDFB8, 0x11d1,
{0xA2, 0xCF, 0x00, 0x80, 0x5F, 0xC7, 0x92, 0x35} };
-const GUID IID_ICOMAdminCatalog = { 0xDD662187, 0xDFC2, 0x11d1,
- {0xA2, 0xCF, 0x00, 0x80, 0x5F, 0xC7, 0x92, 0x35} };
+const GUID IID_ICOMAdminCatalog2 = { 0x790C6E0B, 0x9194, 0x4cc9,
+ {0x94, 0x26, 0xA4, 0x8A, 0x63, 0x18, 0x56, 0x96} };
const GUID CLSID_WbemLocator = { 0x4590f811, 0x1d3a, 0x11d0,
{0x89, 0x1f, 0x00, 0xaa, 0x00, 0x4b, 0x2e, 0x24} };
const GUID IID_IWbemLocator = { 0xdc12a687, 0x737f, 0x11cf,
HRESULT hr;
COMInitializer initializer;
COMPointer<IUnknown> pUnknown;
- COMPointer<ICOMAdminCatalog> pCatalog;
+ COMPointer<ICOMAdminCatalog2> pCatalog;
COMPointer<ICatalogCollection> pColl;
COMPointer<ICatalogObject> pObj;
_variant_t var;
chk(CoCreateInstance(CLSID_COMAdminCatalog, NULL, CLSCTX_INPROC_SERVER,
IID_IUnknown, (void **)pUnknown.replace()));
- chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog,
+ chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog2,
(void **)pCatalog.replace()));
chk(pCatalog->GetCollection(_bstr_t(L"Applications"),
(IDispatch **)pColl.replace()));
HRESULT hr;
COMInitializer initializer;
COMPointer<IUnknown> pUnknown;
- COMPointer<ICOMAdminCatalog> pCatalog;
+ COMPointer<ICOMAdminCatalog2> pCatalog;
COMPointer<ICatalogCollection> pApps, pRoles, pUsersInRole;
COMPointer<ICatalogObject> pObj;
long n;
chk(CoCreateInstance(CLSID_COMAdminCatalog, NULL, CLSCTX_INPROC_SERVER,
IID_IUnknown, (void **)pUnknown.replace()));
- chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog,
+ chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog2,
(void **)pCatalog.replace()));
/* Install COM+ Component */
goto out;
}
+ chk(pCatalog->CreateServiceForApplication(
+ _bstr_t(QGA_PROVIDER_LNAME), _bstr_t(QGA_PROVIDER_LNAME),
+ _bstr_t(L"SERVICE_AUTO_START"), _bstr_t(L"SERVICE_ERROR_NORMAL"),
+ _bstr_t(L""), _bstr_t(L".\\localsystem"), _bstr_t(L""), FALSE));
chk(pCatalog->InstallComponent(_bstr_t(QGA_PROVIDER_LNAME),
_bstr_t(dllPath), _bstr_t(tlbPath),
_bstr_t("")));
if (l > size)
l = size;
memcpy(f->buf + f->buf_index, buf, l);
- f->bytes_xfer += size;
+ f->bytes_xfer += l;
if (f->ops->writev_buffer) {
add_to_iovec(f, f->buf + f->buf_index, l);
}
/* cache info: needed for Core compatibility */
if (cpu->cache_info_passthrough) {
host_cpuid(index, count, eax, ebx, ecx, edx);
- break;
- }
- if (cs->nr_cores > 1) {
- *eax = (cs->nr_cores - 1) << 26;
+ *eax &= ~0xFC000000;
} else {
*eax = 0;
- }
- switch (count) {
+ switch (count) {
case 0: /* L1 dcache info */
*eax |= CPUID_4_TYPE_DCACHE | \
CPUID_4_LEVEL(1) | \
*ecx = 0;
*edx = 0;
break;
+ }
+ }
+
+ /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
+ if ((*eax & 31) && cs->nr_cores > 1) {
+ *eax |= (cs->nr_cores - 1) << 26;
}
break;
case 5:
uint32_t signature[3];
int r;
+ memset(&cpuid_data, 0, sizeof(cpuid_data));
+
cpuid_i = 0;
/* Paravirtualization CPUIDs */
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = KVM_CPUID_SIGNATURE;
if (!hyperv_enabled(cpu)) {
memcpy(signature, "KVMKVMKVM\0\0\0", 12);
c->edx = signature[2];
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = KVM_CPUID_FEATURES;
c->eax = env->features[FEAT_KVM];
c->eax = signature[0];
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = HYPERV_CPUID_VERSION;
c->eax = 0x00001bbc;
c->ebx = 0x00060001;
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = HYPERV_CPUID_FEATURES;
if (cpu->hyperv_relaxed_timing) {
c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
}
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
if (cpu->hyperv_relaxed_timing) {
c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
c->ebx = cpu->hyperv_spinlock_attempts;
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
c->eax = 0x40;
c->ebx = 0x40;
c = &cpuid_data.entries[cpuid_i++];
- memset(c, 0, sizeof(*c));
c->function = KVM_CPUID_SIGNATURE_NEXT;
memcpy(signature, "KVMKVMKVM\0\0\0", 12);
c->eax = 0;
for (i = 0; i < xcrs.nr_xcrs; i++) {
/* Only support xcr0 now */
- if (xcrs.xcrs[0].xcr == 0) {
- env->xcr0 = xcrs.xcrs[0].value;
+ if (xcrs.xcrs[i].xcr == 0) {
+ env->xcr0 = xcrs.xcrs[i].value;
break;
}
}
int scale;
int opreg;
int mod, rm, code, override, must_add_seg;
+ TCGv sum;
override = s->override;
must_add_seg = s->addseg;
rm = modrm & 7;
if (s->aflag) {
-
havesib = 0;
base = rm;
- index = 0;
+ index = -1;
scale = 0;
if (base == 4) {
code = cpu_ldub_code(env, s->pc++);
scale = (code >> 6) & 3;
index = ((code >> 3) & 7) | REX_X(s);
+ if (index == 4) {
+ index = -1; /* no index */
+ }
base = (code & 7);
}
base |= REX_B(s);
break;
}
- if (base >= 0) {
- /* for correct popl handling with esp */
- if (base == 4 && s->popl_esp_hack)
- disp += s->popl_esp_hack;
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(base);
- if (disp != 0) {
- gen_op_addq_A0_im(disp);
- }
- } else
-#endif
- {
- gen_op_movl_A0_reg(base);
- if (disp != 0)
- gen_op_addl_A0_im(disp);
+ /* For correct popl handling with esp. */
+ if (base == R_ESP && s->popl_esp_hack) {
+ disp += s->popl_esp_hack;
+ }
+
+ /* Compute the address, with a minimum number of TCG ops. */
+ TCGV_UNUSED(sum);
+ if (index >= 0) {
+ if (scale == 0) {
+ sum = cpu_regs[index];
+ } else {
+ tcg_gen_shli_tl(cpu_A0, cpu_regs[index], scale);
+ sum = cpu_A0;
}
- } else {
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_im(disp);
- } else
-#endif
- {
- gen_op_movl_A0_im(disp);
+ if (base >= 0) {
+ tcg_gen_add_tl(cpu_A0, sum, cpu_regs[base]);
+ sum = cpu_A0;
}
+ } else if (base >= 0) {
+ sum = cpu_regs[base];
}
- /* index == 4 means no index */
- if (havesib && (index != 4)) {
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_addq_A0_reg_sN(scale, index);
- } else
-#endif
- {
- gen_op_addl_A0_reg_sN(scale, index);
- }
+ if (TCGV_IS_UNUSED(sum)) {
+ tcg_gen_movi_tl(cpu_A0, disp);
+ } else {
+ tcg_gen_addi_tl(cpu_A0, sum, disp);
}
+
if (must_add_seg) {
if (override < 0) {
- if (base == R_EBP || base == R_ESP)
+ if (base == R_EBP || base == R_ESP) {
override = R_SS;
- else
+ } else {
override = R_DS;
+ }
}
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_addq_A0_seg(override);
- } else
-#endif
- {
- gen_op_addl_A0_seg(s, override);
+
+ tcg_gen_ld_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUX86State, segs[override].base));
+ if (CODE64(s)) {
+ if (s->aflag != 2) {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
+ }
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ goto done;
}
+
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ }
+
+ if (s->aflag != 2) {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
} else {
switch (mod) {
}
}
+ done:
opreg = OR_A0;
disp = 0;
*reg_ptr = opreg;
/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
- if (env->flags & D_FLAG) { /* Delay Slot insn */
+
+ env->epcr = env->pc;
+ if (env->flags & D_FLAG) {
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
- env->epcr = env->jmp_pc;
- } else {
- env->epcr = env->pc - 4;
- }
- } else {
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
- env->epcr = env->npc;
- } else {
- env->epcr = env->pc;
- }
+ env->epcr -= 4;
+ }
+ if (env->exception_index == EXCP_SYSCALL) {
+ env->epcr += 4;
}
/* For machine-state changed between user-mode and supervisor mode,
int *prot, target_ulong address, int rw)
{
*physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
if (ret == TLBRET_MATCH) {
tlb_set_page(env, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
} else if (ret < 0) {
case TO_SPR(0, 64): /* ESR */
env->esr = rb;
break;
- case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+ case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
env->tlb->dtlb[0][idx].mr = rb;
break;
- case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+ case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env->tlb->dtlb[0][idx].tr = rb;
break;
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
- case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
+ case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
env->tlb->itlb[0][idx].mr = rb;
break;
- case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+ case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env->tlb->itlb[0][idx].tr = rb;
break;
break;
case TO_SPR(10, 0): /* TTMR */
{
+ if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
+ switch (rb & TTMR_M) {
+ case TIMER_NONE:
+ cpu_openrisc_count_stop(cpu);
+ break;
+ case TIMER_INTR:
+ case TIMER_SHOT:
+ case TIMER_CONT:
+ cpu_openrisc_count_start(cpu);
+ break;
+ default:
+ break;
+ }
+ }
+
int ip = env->ttmr & TTMR_IP;
if (rb & TTMR_IP) { /* Keep IP bit. */
- env->ttmr = (rb & ~TTMR_IP) + ip;
+ env->ttmr = (rb & ~TTMR_IP) | ip;
} else { /* Clear IP bit. */
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
- cpu_openrisc_count_update(cpu);
-
- switch (env->ttmr & TTMR_M) {
- case TIMER_NONE:
- cpu_openrisc_count_stop(cpu);
- break;
- case TIMER_INTR:
- cpu_openrisc_count_start(cpu);
- break;
- case TIMER_SHOT:
- cpu_openrisc_count_start(cpu);
- break;
- case TIMER_CONT:
- cpu_openrisc_count_start(cpu);
- break;
- default:
- break;
- }
+ cpu_openrisc_timer_update(cpu);
}
break;
if (env->ttmr & TIMER_NONE) {
return;
}
- cpu_openrisc_count_start(cpu);
+ cpu_openrisc_timer_update(cpu);
break;
default:
case TO_SPR(0, 64): /* ESR */
return env->esr;
- case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+ case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env->tlb->dtlb[0][idx].mr;
- case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+ case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
return env->tlb->dtlb[0][idx].tr;
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
- case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
+ case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
return env->tlb->itlb[0][idx].mr;
- case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+ case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
return env->tlb->itlb[0][idx].tr;
static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
{
target_ulong tmp_pc;
- int lab = gen_new_label();
- TCGv sr_f = tcg_temp_new();
/* N26, 26bits imm */
tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
- if (op0 == 0x00) { /* l.j */
+ switch (op0) {
+ case 0x00: /* l.j */
tcg_gen_movi_tl(jmp_pc, tmp_pc);
- } else if (op0 == 0x01) { /* l.jal */
+ break;
+ case 0x01: /* l.jal */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_movi_tl(jmp_pc, tmp_pc);
- } else if (op0 == 0x03) { /* l.bnf */
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
- } else if (op0 == 0x04) { /* l.bf */
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
- } else if (op0 == 0x11) { /* l.jr */
+ break;
+ case 0x03: /* l.bnf */
+ case 0x04: /* l.bf */
+ {
+ int lab = gen_new_label();
+ TCGv sr_f = tcg_temp_new();
+ tcg_gen_movi_tl(jmp_pc, dc->pc+8);
+ tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
+ tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
+ sr_f, SR_F, lab);
+ tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ gen_set_label(lab);
+ tcg_temp_free(sr_f);
+ }
+ break;
+ case 0x11: /* l.jr */
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- } else if (op0 == 0x12) { /* l.jalr */
+ break;
+ case 0x12: /* l.jalr */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- } else {
+ break;
+ default:
gen_illegal_exception(dc);
+ break;
}
- tcg_temp_free(sr_f);
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
gen_sync_flags(dc);
}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
case 0x27: /* l.addi */
LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
{
- int lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
- tcg_gen_trunc_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 32);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_ove);
+ if (I16 == 0) {
+ tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
+ } else {
+ int lab = gen_new_label();
+ TCGv_i64 ta = tcg_temp_new_i64();
+ TCGv_i64 td = tcg_temp_local_new_i64();
+ TCGv_i32 res = tcg_temp_local_new_i32();
+ TCGv_i32 sr_ove = tcg_temp_local_new_i32();
+ tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
+ tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
+ tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_shri_i64(td, td, 32);
+ tcg_gen_andi_i64(td, td, 0x3);
+ /* Jump to lab when no overflow. */
+ tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
+ tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
+ tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
+ tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
+ tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
+ gen_exception(dc, EXCP_RANGE);
+ gen_set_label(lab);
+ tcg_gen_mov_i32(cpu_R[rd], res);
+ tcg_temp_free_i64(ta);
+ tcg_temp_free_i64(td);
+ tcg_temp_free_i32(res);
+ tcg_temp_free_i32(sr_ove);
+ }
}
break;
b = 0x01;
c = 0xffffffff;
- result = 1;
+ result = 0;
__asm
- ("l.addc %0, %1, %2\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addc %0, %1, %2\n\t"
: "=r"(a)
: "r"(b), "r"(c)
);
c = 0xffffffff;
result = 0x80000001;
__asm
- ("l.addc %0, %1, %2\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addc %0, %1, %2\n\t"
"l.movhi %2, 0x7fff\n\t"
"l.ori %2, %2, 0xffff\n\t"
"l.addc %0, %1, %2\n\t"
int result;
a = 1;
- result = 0x1;
+ result = 0x0;
__asm
- ("l.addic %0, %0, 0xffff\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addic %0, %0, 0xffff\n\t"
: "+r"(a)
);
if (a != result) {
return -1;
}
- a = 0x1;
+ a = -1;
result = 0x201;
__asm
- ("l.addic %0, %0, 0xffff\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addic %0, %0, 0x1\n\t"
"l.ori %0, r0, 0x100\n\t"
"l.addic %0, %0, 0x100\n\t"
: "+r"(a)