usb: dwc2: Fix call location of dwc2_check_core_endianness

Some SoC/IP as STM32F469, the snpsid can only be read after clock is
enabled, otherwise it will read as 0, and the dwc2_check_core_endianness
will assume the core and AHB have opposite endianness, leading to the
following error:

[    1.976339] dwc2 50000000.usb: 50000000.usb supply vusb_d not found, using dummy regulator
[    1.986124] dwc2 50000000.usb: Linked as a consumer to regulator.0
[    1.992711] dwc2 50000000.usb: 50000000.usb supply vusb_a not found, using dummy regulator
[    2.003672] dwc2 50000000.usb: dwc2_core_reset: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE
[    2.015176] dwc2: probe of 50000000.usb failed with error -16

The proposed patch changes the location where dwc2_check_core_endianness
is called, allowing the clock peripheral to be enabled first.

Acked-by: Minas Harutyunyan <hminas@synopsys.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Bruno Meirelles Herrera <bmh@certi.org.br>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9a53a58e676e0ae775550fb872ed168c65598f84..577642895b57d118eb37115cdb005089ee5c6e08 100644 (file)
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -412,8 +412,6 @@ static int dwc2_driver_probe(struct platform_device *dev)
        dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
                (unsigned long)res->start, hsotg->regs);
 
-       hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
-
        retval = dwc2_lowlevel_hw_init(hsotg);
        if (retval)
                return retval;
@@ -438,6 +436,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
        if (retval)
                return retval;
 
+       hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+
        retval = dwc2_get_dr_mode(hsotg);
        if (retval)
                goto error;