]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/commitdiff
arm64: dts: renesas: r8a77970: eagle/v3msk: Add QSPI flash support
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Fri, 19 Jun 2020 20:22:32 +0000 (23:22 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 13 Jul 2020 08:48:01 +0000 (10:48 +0200)
Define the Eagle/V3MSK board dependent parts of the RPC-IF device node.
Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.

Based on the original patches by Dmitry Shifrin.

Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/fca1d012-29bf-eead-1c0d-4dd837c0bc68@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts

index ac2156ab3e6261749208ddd40fdb8b4687646f21..5c28f303e911343c7c6501ad6bb129cf00fa42e3 100644 (file)
                function = "i2c0";
        };
 
+       qspi0_pins: qspi0 {
+               groups = "qspi0_ctrl", "qspi0_data4";
+               function = "qspi0";
+       };
+
        scif0_pins: scif0 {
                groups = "scif0_data";
                function = "scif0";
        };
 };
 
+&rpc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spansion,s25fs512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <50000000>;
+               spi-rx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       bootparam@0 {
+                               reg = <0x00000000 0x040000>;
+                               read-only;
+                       };
+                       cr7@40000 {
+                               reg = <0x00040000 0x080000>;
+                               read-only;
+                       };
+                       cert_header_sa3@c0000 {
+                               reg = <0x000c0000 0x080000>;
+                               read-only;
+                       };
+                       bl2@140000 {
+                               reg = <0x00140000 0x040000>;
+                               read-only;
+                       };
+                       cert_header_sa6@180000 {
+                               reg = <0x00180000 0x040000>;
+                               read-only;
+                       };
+                       bl31@1c0000 {
+                               reg = <0x001c0000 0x460000>;
+                               read-only;
+                       };
+                       uboot@640000 {
+                               reg = <0x00640000 0x0c0000>;
+                               read-only;
+                       };
+                       uboot-env@700000 {
+                               reg = <0x00700000 0x040000>;
+                               read-only;
+                       };
+                       dtb@740000 {
+                               reg = <0x00740000 0x080000>;
+                       };
+                       kernel@7c0000 {
+                               reg = <0x007c0000 0x1400000>;
+                       };
+                       user@1bc0000 {
+                               reg = <0x01bc0000 0x2440000>;
+                       };
+               };
+       };
+};
+
 &rwdt {
        timeout-sec = <60>;
        status = "okay";
index 01c4ba0f7be1caff29424f39b50e6f63d1048032..668a1ece9af00420c40934004c069e1065fafaee 100644 (file)
                power-source = <3300>;
        };
 
+       qspi0_pins: qspi0 {
+               groups = "qspi0_ctrl", "qspi0_data4";
+               function = "qspi0";
+       };
+
        scif0_pins: scif0 {
                groups = "scif0_data";
                function = "scif0";
        };
 };
 
+&rpc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spansion,s25fs512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <50000000>;
+               spi-rx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       bootparam@0 {
+                               reg = <0x00000000 0x040000>;
+                               read-only;
+                       };
+                       cr7@40000 {
+                               reg = <0x00040000 0x080000>;
+                               read-only;
+                       };
+                       cert_header_sa3@c0000 {
+                               reg = <0x000c0000 0x080000>;
+                               read-only;
+                       };
+                       bl2@140000 {
+                               reg = <0x00140000 0x040000>;
+                               read-only;
+                       };
+                       cert_header_sa6@180000 {
+                               reg = <0x00180000 0x040000>;
+                               read-only;
+                       };
+                       bl31@1c0000 {
+                               reg = <0x001c0000 0x460000>;
+                               read-only;
+                       };
+                       uboot@640000 {
+                               reg = <0x00640000 0x0c0000>;
+                               read-only;
+                       };
+                       uboot-env@700000 {
+                               reg = <0x00700000 0x040000>;
+                               read-only;
+                       };
+                       dtb@740000 {
+                               reg = <0x00740000 0x080000>;
+                       };
+                       kernel@7c0000 {
+                               reg = <0x007c0000 0x1400000>;
+                       };
+                       user@1bc0000 {
+                               reg = <0x01bc0000 0x2440000>;
+                       };
+               };
+       };
+};
+
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";