]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/commitdiff
drm/i915: Include TLB miss overhead for computing WM
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 8 Jan 2011 09:02:21 +0000 (09:02 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:44:54 +0000 (20:44 +0000)
The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_display.c

index 1190efa390bdc7f439bfd352b7554a73f8bd65b5..25d96889d7d245a60a4d9ef15d9279032f73b6fd 100644 (file)
@@ -3425,8 +3425,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev,
                                 int *cursor_wm)
 {
        struct drm_crtc *crtc;
-       int htotal, hdisplay, clock, pixel_size = 0;
-       int line_time_us, line_count, entries;
+       int htotal, hdisplay, clock, pixel_size;
+       int line_time_us, line_count;
+       int entries, tlb_miss;
 
        crtc = intel_get_crtc_for_pipe(dev, pipe);
        if (crtc->fb == NULL || !crtc->enabled)
@@ -3439,6 +3440,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev,
 
        /* Use the small buffer method to calculate plane watermark */
        entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
+       tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
+       if (tlb_miss > 0)
+               entries += tlb_miss;
        entries = DIV_ROUND_UP(entries, display->cacheline_size);
        *plane_wm = entries + display->guard_size;
        if (*plane_wm > (int)display->max_wm)
@@ -3448,6 +3452,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev,
        line_time_us = ((htotal * 1000) / clock);
        line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
        entries = line_count * 64 * pixel_size;
+       tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
+       if (tlb_miss > 0)
+               entries += tlb_miss;
        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
        *cursor_wm = entries + cursor->guard_size;
        if (*cursor_wm > (int)cursor->max_wm)