PCI: mediatek-gen3: Disable DVFSRC voltage request

BugLink: https://bugs.launchpad.net/bugs/1964361
[ Upstream commit ab344fd43f2958726d17d651c0cb692c67dca382 ]

When the DVFSRC (dynamic voltage and frequency scaling resource collector)
feature is not implemented, the PCIe hardware will assert a voltage request
signal when exit from the L1 PM Substates to request a specific Vcore
voltage, but cannot receive the voltage ready signal, which will cause
the link to fail to exit the L1 PM Substates.

Disable DVFSRC voltage request by default, we need to find a common way to
enable it in the future.

Link: https://lore.kernel.org/r/20211015063602.29058-1-jianjun.wang@mediatek.com
Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192")
Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 17c59b0d6978b663e2ff9a5cdac16e2a342ee9de..21207df680ccf3af8d0f6c02ffd121ba938da4d1 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -79,6 +79,9 @@
 #define PCIE_ICMD_PM_REG               0x198
 #define PCIE_TURN_OFF_LINK             BIT(4)
 
+#define PCIE_MISC_CTRL_REG             0x348
+#define PCIE_DISABLE_DVFSRC_VLT_REQ    BIT(1)
+
 #define PCIE_TRANS_TABLE_BASE_REG      0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
        val &= ~PCIE_INTX_ENABLE;
        writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
 
+       /* Disable DVFSRC voltage request */
+       val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
+       val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+       writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG);
+
        /* Assert all reset signals */
        val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
        val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;