drm/nouveau/disp: Support more modes by checking with lower bpc

BugLink: https://bugs.launchpad.net/bugs/2016879
commit 7f67aa097e875c87fba024e850cf405342300059 upstream.

This allows us to advertise more modes especially on HDR displays.

Fixes using 4K@60 modes on my TV and main display both using a HDMI to DP
adapter. Also fixes similar issues for users running into this.

Cc: stable@vger.kernel.org # 5.10+
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230330223938.4025569-1-kherbst@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index ed9d374147b8d11614c3c175f1b659b82607b56c..5bb777ff13130853e9742fefb4e58a44f97356a5 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -363,6 +363,35 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
        return 0;
 }
 
+static void
+nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
+{
+       struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
+       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+       struct drm_display_mode *mode = &asyh->state.adjusted_mode;
+       unsigned int max_rate, mode_rate;
+
+       switch (nv_encoder->dcb->type) {
+       case DCB_OUTPUT_DP:
+               max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
+
+               /* we don't support more than 10 anyway */
+               asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
+
+               /* reduce the bpc until it works out */
+               while (asyh->or.bpc > 6) {
+                       mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
+                       if (mode_rate <= max_rate)
+                               break;
+
+                       asyh->or.bpc -= 2;
+               }
+               break;
+       default:
+               break;
+       }
+}
+
 static int
 nv50_outp_atomic_check(struct drm_encoder *encoder,
                       struct drm_crtc_state *crtc_state,
@@ -381,6 +410,9 @@ nv50_outp_atomic_check(struct drm_encoder *encoder,
        if (crtc_state->mode_changed || crtc_state->connectors_changed)
                asyh->or.bpc = connector->display_info.bpc;
 
+       /* We might have to reduce the bpc */
+       nv50_outp_atomic_fix_depth(encoder, crtc_state);
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index e00876f92aeea582c13642664b4774cf4c5726c8..d49b4875fc3c934fe4d6cd87c0d3b1b3b997088f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -263,8 +263,6 @@ nouveau_dp_irq(struct work_struct *work)
 }
 
 /* TODO:
- * - Use the minimum possible BPC here, once we add support for the max bpc
- *   property.
  * - Validate against the DP caps advertised by the GPU (we don't check these
  *   yet)
  */
@@ -276,7 +274,11 @@ nv50_dp_mode_valid(struct drm_connector *connector,
 {
        const unsigned int min_clock = 25000;
        unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock;
-       const u8 bpp = connector->display_info.bpc * 3;
+       /* Check with the minmum bpc always, so we can advertise better modes.
+        * In particlar not doing this causes modes to be dropped on HDR
+        * displays as we might check with a bpc of 16 even.
+        */
+       const u8 bpp = 6 * 3;
 
        if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
                return MODE_NO_INTERLACE;