drm/amd/powerplay: add atomctrl function to calculate CZ sclk dividers

BugLink: http://bugs.launchpad.net/bugs/1546572
Use atombios to calculate the values.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit d39d5c2c9dcfb9e9aec2be154784a12f5b4a6c97)
Signed-off-by: Alberto Milone <alberto.milone@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index 8b47ea0c8d3e21d84b2ee14314b45e7c855b93fd..ea87c9088b32e1c5f16fec1b387dc696cbbd37f4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -313,6 +313,28 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
        return result;
 }
 
+int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
+                                         uint32_t clock_value,
+                                         pp_atomctrl_clock_dividers_kong *dividers)
+{
+       COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
+       int result;
+
+       pll_parameters.ulClock = clock_value;
+
+       result = cgs_atom_exec_cmd_table
+               (hwmgr->device,
+                GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
+                &pll_parameters);
+
+       if (0 == result) {
+               dividers->pll_post_divider = pll_parameters.ucPostDiv;
+               dividers->real_clock = pll_parameters.ulClock;
+       }
+
+       return result;
+}
+
 int atomctrl_get_engine_pll_dividers_vi(
                struct pp_hwmgr *hwmgr,
                uint32_t clock_value,

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index b5ba37151190713b8631e574a61c9fbfc316ce02..627420b80a5ffa2b8041596509d634f33f65f5cd 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -233,6 +233,9 @@ extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uin
 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
                uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
+extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
+                                                uint32_t clock_value,
+                                                pp_atomctrl_clock_dividers_kong *dividers);
 extern int atomctrl_read_efuse(void *device, uint16_t start_index,
                uint16_t end_index, uint32_t mask, uint32_t *efuse);
 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,