struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
- qemu_irq *isa;
+ qemu_irq *isa_irqs_in;
MC146818RtcState rtc;
PCIIDEState ide;
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
- qemu_set_irq(s->isa[pic_irq], pic_level);
+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
}
}
/* initialize i8259 pic */
i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- s->isa = i8259_init(isa_bus, *i8259_out_irq);
+ s->isa_irqs_in = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
- isa_bus_register_input_irqs(isa_bus, s->isa);
+ isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa_irqs_in[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}