perf/x86/intel: Fix LBR callstack issue caused by FREEZE_LBRS_ON_PMI

This patch fixes an issue which introduced by commit
1a78d93750bb5f61abdc59a91fc3bd06a214542a ("perf/x86/intel: Streamline
LBR MSR handling in PMI").

The old patch not only avoids writing LBR_SELECT MSR in PMI, but also
avoids updating lbr_select variable. So in PMI, FREEZE_LBRS_ON_PMI bit
is always mistakenly set for IA32_DEBUGCTLMSR MSR, which causes
superfluous increase/decrease of LBR_TOS when collecting LBR callstack.

Reported-by: Milian Wolff <mail@milianw.de>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1439815051-8616-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index b2c9475b7ff24af15c08a68f1847eca336bbec97..a1d07c71d3b6179a989efcdd78be914400f69442 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -151,10 +151,9 @@ static void __intel_pmu_lbr_enable(bool pmi)
         * No need to reprogram LBR_SELECT in a PMI, as it
         * did not change.
         */
-       if (cpuc->lbr_sel && !pmi) {
-               lbr_select = cpuc->lbr_sel->config;
+       lbr_select = cpuc->lbr_sel->config;
+       if (cpuc->lbr_sel && !pmi)
                wrmsrl(MSR_LBR_SELECT, lbr_select);
-       }
 
        rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
        orig_debugctl = debugctl;