drm/amdgpu: Make display watermark calculations more accurate

BugLink: http://bugs.launchpad.net/bugs/1694621
commit d63c277dc672e0c568481af043359420fa9d4736 upstream.

Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.

Implemented here for DCE 6,8,10,11.
Successfully tested on DCE 10 with AMD R9 380 Tonga.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index ffe83b648ec22d59d66a70de51271e5050cde614..3a25da4a6e60eef89f28c788aca0db5c7843e2a3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1237,14 +1237,14 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce10_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1259,7 +1259,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1298,7 +1298,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 2944a8fa6b745b37b21073e1d9a86a4c25433e24..d6d3cda77762bafb51f0e2a8185f4fb4a6aa90cd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1225,14 +1225,14 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce10_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1247,7 +1247,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1286,7 +1286,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index e378a70f1b61485249057fd3ab14eeb3b177e1e2..d6e51d4b04f08b389da22156222f56930de7c751 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1207,14 +1207,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 {
        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
        struct dce8_wm_params wm_low, wm_high;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                /* watermark for high clocks */
                if (adev->pm.dpm_enabled) {
@@ -1229,7 +1229,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1268,7 +1268,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)