clk: xgene: Add missing parenthesis when clearing divider value

BugLink: http://bugs.launchpad.net/bugs/1631468
commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 266d573b91342d38ed0d72645dc149a14cc7e3c1..9b081301b026740196405e279b8c03bb71fed429 100644 (file)
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -376,8 +376,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                /* Set new divider */
                data = xgene_clk_read(pclk->param.divider_reg +
                                pclk->param.reg_divider_offset);
-               data &= ~((1 << pclk->param.reg_divider_width) - 1)
-                               << pclk->param.reg_divider_shift;
+               data &= ~(((1 << pclk->param.reg_divider_width) - 1)
+                               << pclk->param.reg_divider_shift);
                data |= divider;
                xgene_clk_write(data, pclk->param.divider_reg +
                                        pclk->param.reg_divider_offset);