Merge remote-tracking branch 'upstream' into memory/batch

* upstream: (87 commits)
  target-alpha: Fix compilation errors for 32 bit hosts
  target-alpha: Add high-resolution access to wall clock and an alarm.
  target-alpha: Implement HALT IPR.
  target-alpha: Implement WAIT IPR.
  target-alpha: Add CLIPPER emulation.
  target-alpha: Add custom PALcode image for CLIPPER emulation.
  target-alpha: Honor icount for RPCC instruction.
  tcg/s390: Remove unused tcg_out_addi()
  tcg/ia64: Remove unused tcg_out_addi()
  ARM: fix segfault
  ppc64: Fix linker script
  pseries: Implement set-time-of-day RTAS function
  pseries: Refactor spapr irq allocation
  PPC: Clean up BookE timer code
  PPC: booke timers
  KVM: PPC: Use HIOR setting for -M pseries with PR KVM
  KVM: Update kernel headers
  KVM: Update kernel headers
  PPC: Fix heathrow PIC to use little endian MMIO
  PPC: Fix via-cuda memory registration
  ...

Conflicts:
	hw/milkymist-uart.c
	hw/ppce500_mpc8544ds.c

Signed-off-by: Avi Kivity <avi@redhat.com>

diff --cc hw/etraxfs_dma.c
Simple merge

diff --cc hw/milkymist-uart.c
index 128cd8cc3862f3a07d65fc6eca20d7fdd759aae9,d836462e4b8c847ada823adc9b89f58e5361f24d..5404ca998cf9811f77559eb7f0f278d9eed9da2e
--- 1/hw/milkymist-uart.c
--- 2/hw/milkymist-uart.c
+++ b/hw/milkymist-uart.c
@@@ -33,20 -36,48 +36,50 @@@ enum 
      R_MAX
  };
  
+ enum {
+     STAT_THRE   = (1<<0),
+     STAT_RX_EVT = (1<<1),
+     STAT_TX_EVT = (1<<2),
+ };
+ 
+ enum {
+     CTRL_RX_IRQ_EN = (1<<0),
+     CTRL_TX_IRQ_EN = (1<<1),
+     CTRL_THRU_EN   = (1<<2),
+ };
+ 
+ enum {
+     DBG_BREAK_EN = (1<<0),
+ };
+ 
  struct MilkymistUartState {
      SysBusDevice busdev;
 +    MemoryRegion regs_region;
      CharDriverState *chr;
- 
-     qemu_irq rx_irq;
-     qemu_irq tx_irq;
+     qemu_irq irq;
  
      uint32_t regs[R_MAX];
  };
  typedef struct MilkymistUartState MilkymistUartState;
  
 -static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+ static void uart_update_irq(MilkymistUartState *s)
+ {
+     int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
+     int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
+     int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
+     int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
+ 
+     if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
+         trace_milkymist_uart_raise_irq();
+         qemu_irq_raise(s->irq);
+     } else {
+         trace_milkymist_uart_lower_irq();
+         qemu_irq_lower(s->irq);
+     }
+ }
+ 
 +static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
 +                          unsigned size)
  {
      MilkymistUartState *s = opaque;
      uint32_t r = 0;
@@@ -95,16 -136,20 +139,18 @@@ static void uart_write(void *opaque, ta
                  TARGET_FMT_plx, addr << 2);
          break;
      }
+ 
+     uart_update_irq(s);
  }
  
 -static CPUReadMemoryFunc * const uart_read_fn[] = {
 -    NULL,
 -    NULL,
 -    &uart_read,
 -};
 -
 -static CPUWriteMemoryFunc * const uart_write_fn[] = {
 -    NULL,
 -    NULL,
 -    &uart_write,
 +static const MemoryRegionOps uart_mmio_ops = {
 +    .read = uart_read,
 +    .write = uart_write,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +    .endianness = DEVICE_NATIVE_ENDIAN,
  };
  
  static void uart_rx(void *opaque, const uint8_t *buf, int size)
@@@ -138,13 -191,13 +192,12 @@@ static void milkymist_uart_reset(Device
  static int milkymist_uart_init(SysBusDevice *dev)
  {
      MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
 -    int uart_regs;
  
-     sysbus_init_irq(dev, &s->rx_irq);
-     sysbus_init_irq(dev, &s->tx_irq);
+     sysbus_init_irq(dev, &s->irq);
  
 -    uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
 -            DEVICE_NATIVE_ENDIAN);
 -    sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
 +    memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
 +            "milkymist-uart", R_MAX * 4);
 +    sysbus_init_mmio_region(dev, &s->regs_region);
  
      s->chr = qdev_init_chardev(&dev->qdev);
      if (s->chr) {

diff --cc hw/openpic.c
index 88e997ebaab0d272bc5815e33061b2bc5703419d,43b8f275d6740233e83a8bfde9700e18d3a0a092..22fc275b626d940398c22ede174437af37b3438c
--- 1/hw/openpic.c
--- 2/hw/openpic.c
+++ b/hw/openpic.c
@@@ -1541,140 -1570,121 +1574,136 @@@ static uint32_t mpic_src_msi_read (voi
      return retval;
  }
  
 -static CPUWriteMemoryFunc * const mpic_glb_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &openpic_gbl_write,
 -};
 -
 -static CPUReadMemoryFunc * const mpic_glb_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &openpic_gbl_read,
 -};
 -
 -static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &mpic_timer_write,
 +static const MemoryRegionOps mpic_glb_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   openpic_gbl_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   openpic_gbl_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUReadMemoryFunc * const mpic_tmr_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &mpic_timer_read,
 +static const MemoryRegionOps mpic_tmr_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   mpic_timer_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   mpic_timer_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &openpic_cpu_write,
 +static const MemoryRegionOps mpic_cpu_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   openpic_cpu_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   openpic_cpu_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUReadMemoryFunc * const mpic_cpu_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &openpic_cpu_read,
 +static const MemoryRegionOps mpic_ext_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   mpic_src_ext_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   mpic_src_ext_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUWriteMemoryFunc * const mpic_ext_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &mpic_src_ext_write,
 +static const MemoryRegionOps mpic_int_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   mpic_src_int_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   mpic_src_int_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUReadMemoryFunc * const mpic_ext_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &mpic_src_ext_read,
 +static const MemoryRegionOps mpic_msg_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   mpic_src_msg_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   mpic_src_msg_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUWriteMemoryFunc * const mpic_int_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &mpic_src_int_write,
 +static const MemoryRegionOps mpic_msi_ops = {
 +    .old_mmio = {
 +        .write = { openpic_buggy_write,
 +                   openpic_buggy_write,
 +                   mpic_src_msi_write,
 +        },
 +        .read  = { openpic_buggy_read,
 +                   openpic_buggy_read,
 +                   mpic_src_msi_read,
 +        },
 +    },
 +    .endianness = DEVICE_BIG_ENDIAN,
  };
  
 -static CPUReadMemoryFunc * const mpic_int_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &mpic_src_int_read,
 -};
 -
 -static CPUWriteMemoryFunc * const mpic_msg_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &mpic_src_msg_write,
 -};
 -
 -static CPUReadMemoryFunc * const mpic_msg_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &mpic_src_msg_read,
 -};
 -static CPUWriteMemoryFunc * const mpic_msi_write[] = {
 -    &openpic_buggy_write,
 -    &openpic_buggy_write,
 -    &mpic_src_msi_write,
 -};
 -
 -static CPUReadMemoryFunc * const mpic_msi_read[] = {
 -    &openpic_buggy_read,
 -    &openpic_buggy_read,
 -    &mpic_src_msi_read,
 -};
 -
 -qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
 -                        qemu_irq **irqs, qemu_irq irq_out)
 +qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
 +                     int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
  {
 -    openpic_t *mpp;
 -    int i;
 +    openpic_t    *mpp;
 +    int           i;
      struct {
 -        CPUReadMemoryFunc * const *read;
 -        CPUWriteMemoryFunc * const *write;
 -        target_phys_addr_t start_addr;
 -        ram_addr_t size;
 +        const char             *name;
 +        MemoryRegionOps const  *ops;
 +        target_phys_addr_t      start_addr;
 +        ram_addr_t              size;
      } const list[] = {
 -        {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
 -        {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
 -        {mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
 -        {mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
 -        {mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
 -        {mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
 -        {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
 +        {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
 +        {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
 +        {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
 +        {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
 +        {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
 +        {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
 +        {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
      };
  
-     /* XXX: for now, only one CPU is supported */
-     if (nb_cpus != 1)
-         return NULL;
- 
      mpp = g_malloc0(sizeof(openpic_t));
  
 +    memory_region_init(&mpp->mem, "mpic", 0x40000);
 +    memory_region_add_subregion(address_space, base, &mpp->mem);
 +
      for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
 -        int mem_index;
  
 -        mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
 -                                           DEVICE_BIG_ENDIAN);
 -        if (mem_index < 0) {
 -            goto free;
 -        }
 -        cpu_register_physical_memory(base + list[i].start_addr,
 -                                     list[i].size, mem_index);
 +        memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
 +                              list[i].name, list[i].size);
 +
 +        memory_region_add_subregion(&mpp->mem, list[i].start_addr,
 +                                    &mpp->sub_io_mem[i]);
      }
  
      mpp->nb_cpus = nb_cpus;

diff --cc hw/ppc405_boards.c
Simple merge

diff --cc hw/ppc440_bamboo.c
Simple merge

diff --cc hw/ppce500_mpc8544ds.c
index 28acf0b1dffec0084bb7e5cf45b8b5737ddc0117,f00367ed7b7b2c74ef041e1d9c5349750f4fc026..5bf8eab897df72753d29279af86d63e64fde54ac
--- 1/hw/ppce500_mpc8544ds.c
--- 2/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@@ -226,9 -227,8 +228,9 @@@ static void mpc8544ds_init(ram_addr_t r
                           const char *initrd_filename,
                           const char *cpu_model)
  {
 +    MemoryRegion *address_space_mem = get_system_memory();
      PCIBus *pci_bus;
-     CPUState *env;
+     CPUState *env = NULL;
      uint64_t elf_entry;
      uint64_t elf_lowaddr;
      target_phys_addr_t entry=0;
@@@ -269,10 -293,11 +295,12 @@@
                                   "mpc8544ds.ram", ram_size));
  
      /* MPIC */
-     irqs = g_malloc0(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
-     irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
-     irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
-     mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
 -    mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL);
++    mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
++                     smp_cpus, irqs, NULL);
+ 
+     if (!mpic) {
+         cpu_abort(env, "MPIC failed to initialize\n");
+     }
  
      /* Serial */
      if (serial_hds[0]) {

diff --cc hw/virtex_ml507.c
Simple merge