Also, adjust cacheline parameter of RW_DATA_SECTION and EXCEPTION_TABLE
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Acked-by: Arnd Bergmann <arnd@arndb.de>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/page.h>
+#include <asm/cache.h>
OUTPUT_ARCH(unicore32)
ENTRY(stext)
HEAD_TEXT_SECTION
INIT_TEXT_SECTION(PAGE_SIZE)
INIT_DATA_SECTION(16)
- PERCPU(PAGE_SIZE)
+ PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
__init_end = .;
_stext = .;
_sdata = .;
RO_DATA_SECTION(PAGE_SIZE)
- RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
+ RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
_edata = .;
- EXCEPTION_TABLE(32)
+ EXCEPTION_TABLE(L1_CACHE_BYTES)
NOTES
BSS_SECTION(0, 0, 0)