i40e/i40evf: check AQ register for valid data

B0 Si blocks AQ registers when in Blank Flash mode - write is dropped,
read gives 0xDEADBEEF. Introduce a simple check for a correct value in one
of the AQ registers to be sure that AQ was configured correctly.
Without this check we get into an endless loop while trying to send
GetVersion AQ cmd.

Change-ID: I00102b8c5fa6c16d14289be677aafadf87f10f0d
Signed-off-by: Kamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
index ba2811be8be42a037787f86b0583a5acb20892bf..7a027499fc57fc968d9ca33df5c65bb9e6825123 100644 (file)
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
@@ -291,8 +291,11 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
  *
  *  Configure base address and length registers for the transmit queue
  **/
-static void i40e_config_asq_regs(struct i40e_hw *hw)
+static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
 {
+       i40e_status ret_code = 0;
+       u32 reg = 0;
+
        if (hw->mac.type == I40E_MAC_VF) {
                /* configure the transmit queue */
                wr32(hw, I40E_VF_ATQBAH1,
@@ -301,6 +304,7 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.asq.desc_buf.pa));
                wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
                                          I40E_VF_ATQLEN1_ATQENABLE_MASK));
+               reg = rd32(hw, I40E_VF_ATQBAL1);
        } else {
                /* configure the transmit queue */
                wr32(hw, I40E_PF_ATQBAH,
@@ -309,7 +313,14 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.asq.desc_buf.pa));
                wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
                                          I40E_PF_ATQLEN_ATQENABLE_MASK));
+               reg = rd32(hw, I40E_PF_ATQBAL);
        }
+
+       /* Check one register to verify that config was applied */
+       if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
+               ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
+
+       return ret_code;
 }
 
 /**
@@ -318,8 +329,11 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
  *
  * Configure base address and length registers for the receive (event queue)
  **/
-static void i40e_config_arq_regs(struct i40e_hw *hw)
+static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
 {
+       i40e_status ret_code = 0;
+       u32 reg = 0;
+
        if (hw->mac.type == I40E_MAC_VF) {
                /* configure the receive queue */
                wr32(hw, I40E_VF_ARQBAH1,
@@ -328,6 +342,7 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.arq.desc_buf.pa));
                wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
                                          I40E_VF_ARQLEN1_ARQENABLE_MASK));
+               reg = rd32(hw, I40E_VF_ARQBAL1);
        } else {
                /* configure the receive queue */
                wr32(hw, I40E_PF_ARQBAH,
@@ -336,10 +351,17 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.arq.desc_buf.pa));
                wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
                                          I40E_PF_ARQLEN_ARQENABLE_MASK));
+               reg = rd32(hw, I40E_PF_ARQBAL);
        }
 
        /* Update tail in the HW to post pre-allocated buffers */
        wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
+
+       /* Check one register to verify that config was applied */
+       if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
+               ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
+
+       return ret_code;
 }
 
 /**
@@ -387,7 +409,9 @@ static i40e_status i40e_init_asq(struct i40e_hw *hw)
                goto init_adminq_free_rings;
 
        /* initialize base registers */
-       i40e_config_asq_regs(hw);
+       ret_code = i40e_config_asq_regs(hw);
+       if (ret_code)
+               goto init_adminq_free_rings;
 
        /* success! */
        goto init_adminq_exit;
@@ -444,7 +468,9 @@ static i40e_status i40e_init_arq(struct i40e_hw *hw)
                goto init_adminq_free_rings;
 
        /* initialize base registers */
-       i40e_config_arq_regs(hw);
+       ret_code = i40e_config_arq_regs(hw);
+       if (ret_code)
+               goto init_adminq_free_rings;
 
        /* success! */
        goto init_adminq_exit;

diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
index 68b4aacd43f534b941cec1127f063eb5a2415996..eb67cce3e8f9a1bed6a0eabfaaeb7067acd703ef 100644 (file)
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
@@ -289,8 +289,11 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
  *
  *  Configure base address and length registers for the transmit queue
  **/
-static void i40e_config_asq_regs(struct i40e_hw *hw)
+static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
 {
+       i40e_status ret_code = 0;
+       u32 reg = 0;
+
        if (hw->mac.type == I40E_MAC_VF) {
                /* configure the transmit queue */
                wr32(hw, I40E_VF_ATQBAH1,
@@ -299,6 +302,7 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.asq.desc_buf.pa));
                wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
                                          I40E_VF_ATQLEN1_ATQENABLE_MASK));
+               reg = rd32(hw, I40E_VF_ATQBAL1);
        } else {
                /* configure the transmit queue */
                wr32(hw, I40E_PF_ATQBAH,
@@ -307,7 +311,14 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.asq.desc_buf.pa));
                wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
                                          I40E_PF_ATQLEN_ATQENABLE_MASK));
+               reg = rd32(hw, I40E_PF_ATQBAL);
        }
+
+       /* Check one register to verify that config was applied */
+       if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
+               ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
+
+       return ret_code;
 }
 
 /**
@@ -316,8 +327,11 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
  *
  * Configure base address and length registers for the receive (event queue)
  **/
-static void i40e_config_arq_regs(struct i40e_hw *hw)
+static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
 {
+       i40e_status ret_code = 0;
+       u32 reg = 0;
+
        if (hw->mac.type == I40E_MAC_VF) {
                /* configure the receive queue */
                wr32(hw, I40E_VF_ARQBAH1,
@@ -326,6 +340,7 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.arq.desc_buf.pa));
                wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
                                          I40E_VF_ARQLEN1_ARQENABLE_MASK));
+               reg = rd32(hw, I40E_VF_ARQBAL1);
        } else {
                /* configure the receive queue */
                wr32(hw, I40E_PF_ARQBAH,
@@ -334,10 +349,17 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
                    lower_32_bits(hw->aq.arq.desc_buf.pa));
                wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
                                          I40E_PF_ARQLEN_ARQENABLE_MASK));
+               reg = rd32(hw, I40E_PF_ARQBAL);
        }
 
        /* Update tail in the HW to post pre-allocated buffers */
        wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
+
+       /* Check one register to verify that config was applied */
+       if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
+               ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
+
+       return ret_code;
 }
 
 /**
@@ -385,7 +407,9 @@ static i40e_status i40e_init_asq(struct i40e_hw *hw)
                goto init_adminq_free_rings;
 
        /* initialize base registers */
-       i40e_config_asq_regs(hw);
+       ret_code = i40e_config_asq_regs(hw);
+       if (ret_code)
+               goto init_adminq_free_rings;
 
        /* success! */
        goto init_adminq_exit;
@@ -442,7 +466,9 @@ static i40e_status i40e_init_arq(struct i40e_hw *hw)
                goto init_adminq_free_rings;
 
        /* initialize base registers */
-       i40e_config_arq_regs(hw);
+       ret_code = i40e_config_arq_regs(hw);
+       if (ret_code)
+               goto init_adminq_free_rings;
 
        /* success! */
        goto init_adminq_exit;