MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+ MV_V2_PORT_MAC_TYPE_MASK = 0x7,
+ MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
struct mv3310_priv {
u32 firmware_ver;
+ bool rate_match;
struct device *hwmon_dev;
char *hwmon_name;
static int mv3310_config_init(struct phy_device *phydev)
{
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
int err;
+ int val;
/* Check that the PHY interface type is compatible */
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
if (err)
return err;
+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
+ if (val < 0)
+ return val;
+ priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
+ MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
}
static void mv3310_update_interface(struct phy_device *phydev)
{
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+
+ /* In "XFI with Rate Matching" mode the PHY interface is fixed at
+ * 10Gb. The PHY adapts the rate to actual wire speed with help of
+ * internal 16KB buffer.
+ */
+ if (priv->rate_match) {
+ phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+ return;
+ }
+
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&