drm/amd/display: clean up encoding checks

[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 70eb9472ccd9fe47a38ec868d38d1f2133dfabf5..366bc8c2c643dd0383a4f5643daf06f64da164f3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -665,21 +665,7 @@ bool dce110_link_encoder_validate_dp_output(
        if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
                return false;
 
-       /* default RGB only */
-       if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-               return true;
-
-       if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
-               return true;
-
-       /* for DCE 8.x or later DP Y-only feature,
-        * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
-       if (crtc_timing->flags.Y_ONLY &&
-               enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
-               crtc_timing->display_color_depth != COLOR_DEPTH_666)
-               return true;
-
-       return false;
+       return true;
 }
 
 void dce110_link_encoder_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index b1cc38827f090ca6f343ecae1fb35c588f5831a0..5b75460525ac41d1354c305d63daf061d84dba2d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -551,8 +551,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_deep_color = COLOR_DEPTH_121212,
                .max_hdmi_pixel_clock = 300000,
                .flags.bits.IS_HBR2_CAPABLE = true,
-               .flags.bits.IS_TPS3_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
+               .flags.bits.IS_TPS3_CAPABLE = true
 };
 
 struct link_encoder *dce100_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index b44cc70422490dc6725e547fd1dda7bb1f8ff1db..4607a6af445162b75964421373fdb99061b55184 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -570,8 +570,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_deep_color = COLOR_DEPTH_121212,
                .max_hdmi_pixel_clock = 594000,
                .flags.bits.IS_HBR2_CAPABLE = true,
-               .flags.bits.IS_TPS3_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
+               .flags.bits.IS_TPS3_CAPABLE = true
 };
 
 static struct link_encoder *dce110_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 0f8332ea1160969a25fc3818808ea5f53e127cb1..8b5a2696a4e82926ee3d330d3f1fc7612b0ad30f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -555,8 +555,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .flags.bits.IS_HBR2_CAPABLE = true,
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,
-               .flags.bits.IS_TPS4_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
+               .flags.bits.IS_TPS4_CAPABLE = true
 };
 
 struct link_encoder *dce112_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 59055801af4442cb7fd7ce0b46608382acb76cbe..53a7a2f2ef76dba0f26bb0d539a48d444113db9d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -609,7 +609,6 @@ static const struct encoder_feature_support link_enc_feature = {
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,
                .flags.bits.IS_TPS4_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
 };
 
 static struct link_encoder *dce120_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 1dc590ccc5f984589217a386a639d36df10582e9..79e5c5c0de5604ddc1714068c8b346f1f0c17bb8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -650,8 +650,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_deep_color = COLOR_DEPTH_121212,
                .max_hdmi_pixel_clock = 297000,
                .flags.bits.IS_HBR2_CAPABLE = true,
-               .flags.bits.IS_TPS3_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
+               .flags.bits.IS_TPS3_CAPABLE = true
 };
 
 struct link_encoder *dce80_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index bef0011a98b09f2a9d289e81223bb75d0b49b5e8..ba6a8686062f27e235799e44eaf95d4d03d39778 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -609,22 +609,7 @@ bool dcn10_link_encoder_validate_dp_output(
        if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
                return false;
 
-       /* default RGB only */
-       if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-               return true;
-
-       if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
-               return true;
-
-       /* for DCE 8.x or later DP Y-only feature,
-        * we need ASIC cap + FeatureSupportDPYonly, not support 666
-        */
-       if (crtc_timing->flags.Y_ONLY &&
-               enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
-               crtc_timing->display_color_depth != COLOR_DEPTH_666)
-               return true;
-
-       return false;
+       return true;
 }
 
 void dcn10_link_encoder_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 97b1cfc012acc3fdcb35279a748c1c94dfba8a6c..affadd7bfe8d1cc7c71c7e520af89bef3274a6ff 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -711,8 +711,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .flags.bits.IS_HBR2_CAPABLE = true,
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,
-               .flags.bits.IS_TPS4_CAPABLE = true,
-               .flags.bits.IS_YCBCR_CAPABLE = true
+               .flags.bits.IS_TPS4_CAPABLE = true
 };
 
 struct link_encoder *dcn10_link_encoder_create(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 58818920ed4175a571d4d5ef135b29b5d1ad864b..e28e9770e0a3638cca907b213a63aceb5787588e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -58,7 +58,6 @@ struct encoder_feature_support {
                        uint32_t IS_HBR3_CAPABLE:1;
                        uint32_t IS_TPS3_CAPABLE:1;
                        uint32_t IS_TPS4_CAPABLE:1;
-                       uint32_t IS_YCBCR_CAPABLE:1;
                        uint32_t HDMI_6GB_EN:1;
                } bits;
                uint32_t raw;