]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashing
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 11 Dec 2023 22:16:36 +0000 (00:16 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 13 Dec 2023 18:49:18 +0000 (20:49 +0200)
Currently we have a hardcoded assumption that the cdclk divider
(2*cd2x divider) is always 2 when squashing is used. While that
is true for all current platforms it might not hold in the future.
So eliminate the assumption and calculate the correct divider
from the other parameters.

v2: s/cd2x divider/cdclk divider/ (Gustavo)
    s/clock/unsquashed_cdclk/ (Gustavo)

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211221636.29658-1-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c

index a1660c6b86ecf299dd33f504d86af0bdb3f6b618..a12cf085dbdb45c6fce1d37278633cbf99caf935 100644 (file)
@@ -1880,9 +1880,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 {
        int cdclk = cdclk_config->cdclk;
        int vco = cdclk_config->vco;
-       u32 val;
+       int unsquashed_cdclk;
        u16 waveform;
-       int clock;
+       u32 val;
 
        if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
            !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
@@ -1899,15 +1899,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
 
        waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-       if (waveform)
-               clock = vco / 2;
-       else
-               clock = cdclk;
+       unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,
+                                            cdclk_squash_divider(waveform));
 
        if (HAS_CDCLK_SQUASH(dev_priv))
                dg2_cdclk_squash_program(dev_priv, waveform);
 
-       val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
+       val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) |
                bxt_cdclk_cd2x_pipe(dev_priv, pipe);
 
        /*